US20090175114A1 - Multi-port semiconductor memory device having variable access paths and method therefor - Google Patents
Multi-port semiconductor memory device having variable access paths and method therefor Download PDFInfo
- Publication number
- US20090175114A1 US20090175114A1 US12/401,766 US40176609A US2009175114A1 US 20090175114 A1 US20090175114 A1 US 20090175114A1 US 40176609 A US40176609 A US 40176609A US 2009175114 A1 US2009175114 A1 US 2009175114A1
- Authority
- US
- United States
- Prior art keywords
- input
- bank
- memory
- output port
- command signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1802—Address decoder
Definitions
- the invention relates to multi-port semiconductor memory devices having variable access paths and, more particularly, to a semiconductor memory device and a method for performing a normal operation or a test operation by variably controlling access paths between a plurality of input/output ports and a plurality of memory areas.
- semiconductor memory devices such as random access memories (RAMs) include one port having a number of input/output pin sets in order to communicate with an external processor.
- RAMs random access memories
- FIG. 1 illustrates a conventional semiconductor memory device having four memory banks and a single input/output port.
- the conventional semiconductor memory device includes a memory array 10 having four memory banks 10 a , 10 b , 10 c and 10 d , and a port control unit 20 for controlling a single input/output port.
- the port control unit 20 includes control circuits for controlling a command signal, an address signal, a data signal, and other signals input or output through the input/output port. All of the memory banks 10 a , 10 b , 10 c and 10 d are accessed through the port control unit 20 .
- the arrows indicate the access paths.
- the conventional semiconductor memory device having a single input/output port has problems with access speed and access efficiency. For example, to perform a first operation of storing first data in the A bank 10 a and a second operation of reading second data from the B bank, which is distinct from the first operation, the semiconductor memory device must perform the operations sequentially, the first operation and then the second operation or vice versa. This is not suitable for high speed and high efficiency.
- a multi-port semiconductor memory device that performs communication through a plurality of processors and has memory cells that can be accessed through a plurality of input/output ports has been developed.
- An example of such a conventional multi-port semiconductor memory device is disclosed in U.S. Pat. No. 5,815,456, Sep. 29, 1998.
- the conventional multi-port semiconductor memory device may have several structures to enable accessing of memory cells.
- Three representative structures include: (1) a structure allowing all memory cells to be accessed through any of a plurality of input/output ports; (2) a structure allowing each memory cell to be accessed only through fixed input/output ports; and (3) a structure allowing specific memory cells to be accessed only through fixed input/output ports and any remaining memory cells to be accessed through any ports.
- One aspect of the invention is a semiconductor memory device having a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to establish variable access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
- a method for variably accessing the memory areas includes allocating the memory areas for access through at least one of the input/output ports and establishing data and address paths between the memory areas and corresponding input/output ports according to the memory area allocation.
- the method further includes re-applying the external command signals to re-allocate the memory areas for access through different input/output ports and establishing new data and address paths between the memory areas and the different input/output ports according to the memory area re-allocation.
- Yet another aspect of the invention provides a method for testing a multi-port semiconductor memory device comprising a plurality of input/output ports and a memory array divided into a plurality of memory areas, the method including: allocating the memory areas to each input/output port, so that each memory area is accessed through at least one of the input/output ports; and testing the allocated memory areas through each corresponding input/output port.
- the method for testing may further include re-allocating the memory areas, so that each memory area is access through different input/output ports; and testing the re-allocated memory areas through the corresponding different input/output ports.
- FIG. 1 illustrates access paths of a conventional semiconductor memory device having four memory banks and a single input/output port
- FIG. 2 is a schematic block diagram illustrating a multi-port semiconductor memory device according to an embodiment of the invention
- FIG. 3 is a block diagram illustrating a select control unit 400 a and first and second port control units 200 a and 300 a for an A bank in FIG. 2 ;
- FIG. 4 is a circuit diagram of a first command multiplexer of FIG. 3 ;
- FIG. 5 is a circuit diagram illustrating a row address multiplexer of FIG. 3 ;
- FIG. 6 is a circuit diagram illustrating a first data sense amplifier of FIG. 3 ;
- FIG. 7 is a circuit diagram illustrating a first data driver of FIG. 3 ;
- FIG. 8 is a circuit diagram illustrating a first data multiplexer of FIG. 3 ;
- FIGS. 9 to 15 illustrate an example of an access path control operation in a semiconductor memory device according to an embodiment of the invention.
- FIG. 2 is a schematic block diagram illustrating a multi-port semiconductor memory device according to an embodiment of the invention.
- the multi-port semiconductor memory device includes a memory array 100 , a first port control unit 200 for controlling signals input or output through a first input/output port, a second port control unit 300 for controlling signals input or output through a second input/output port different from the first input/output port, and a select control unit 400 .
- the memory array 100 is divided into a plurality of different memory areas.
- the memory array may be divided into four memory banks 100 a , 100 b , 100 c and 100 d , as in a typical semiconductor memory device.
- first port control unit 200 and the second port control unit 300 include the first input/output port and the second input/output port, respectively.
- the first port control unit 200 includes control circuits for controlling a command signal, an address signal, a data signal, and other signals input or output through the first input/output port.
- the second port control unit 300 includes control circuits for controlling a command signal, an address signal, a data signal, and other signals input or output through the second input/output port.
- the select control unit 400 performs a memory allocation operation that controls a data path and an address path between the input/output ports and the memory areas constituting the memory array 100 . That is, the select control unit 400 preferably controls access paths between the memory areas and the input/output ports so that each memory area may be variably accessed through at least one of the input/output ports. For example, the select control unit 400 controls the access path to variably allocate each of the four memory banks 100 a , 100 b , 100 c and 100 d as one of a first input/output port dedicated access area, a second input/output port dedicated access area, and a shared access area.
- the select control unit 400 may perform a memory allocation operation in response to a mode register set (MRS) signal for a normal operation and in response to an MRS signal for a test operation.
- the select control unit 400 may also operate in response to a command signal generated by any external command signals normally applied for operation of the semiconductor memory device or a combination of the external command signals, which are not the MRS signal.
- the external command signals may be separate, independent signals that each correspond to the memory areas.
- FIG. 3 is a block diagram illustrating an example of a select control unit 400 a and first and second port control units 200 a and 300 a for allocating one memory bank (e.g., A bank 100 a ) to the first or second input/output port in FIG. 2 .
- a select control unit 400 a and first and second port control units 200 a and 300 a shown in FIG. 3 are for only one memory bank (e.g., A bank 100 a ). Accordingly, as will be appreciated by those skilled in the art, if the semiconductor memory device has a plurality of memory banks, a select control unit and port control units for each memory bank may be similarly configured as the select control unit 400 a and the first and second port control units 200 a and 300 a.
- the A bank 100 a in the memory array 100 of FIGS. 2 and 3 may refer to one of a plurality of memory banks in a typical semiconductor memory device.
- the A bank 100 a may also refer to an internal sub block constituting a memory bank, which is a smaller unit than a typical memory bank.
- the A bank 100 a may also refer to a combination of two or more memory banks.
- Each memory cell in the A bank 100 is selected by one of word lines WL and one of bit lines BL.
- a row decoder 110 for selecting the word line WL in the A bank 100 a and a column decoder 120 for selecting the bit line BL in the A bank 100 a are provided around the A bank 100 a.
- the first port control unit 200 a includes a first data sense amplifier 210 and a first data driver 220 for controlling data input to or output from the A bank through the first input/output port.
- the first port control unit 200 a may additionally include a data buffer circuit or a latch circuit for controlling data input and output.
- the first port control unit 200 a may further include control circuits (e.g., command buffer circuit, command latch circuit, address latch circuit, and address buffer circuit) for controlling command signals (e.g., bank select signal CMD_A 1 , RAS signal, CAS signal, write command signal, and read command signal) and the address signal ADD_ 1 input through the first input/output port.
- command signals e.g., bank select signal CMD_A 1 , RAS signal, CAS signal, write command signal, and read command signal
- the address signal ADD_ 1 input through the first input/output port.
- the first data sense amplifier 210 is for read operation of data Dout_ 1 stored in the A bank 100 a and outputting data Dout_ 1
- the first data driver 220 is for write operation of external input data Din_ 1 and storing data Din_ 1 in the A bank 100 a.
- the second port control unit 300 a includes a second data sense amplifier 310 and a second data driver 320 for controlling data input to or output from the A bank through the second input/output port.
- the second port control unit 300 a may additionally include a data buffer circuit or a latch circuit for controlling data input and output.
- the second port control unit 300 a may further include control circuits (e.g., command buffer circuit, command latch circuit, address latch circuit, and address buffer circuit) for controlling command signals (e.g., bank select signal CMD_A 2 , RAS signal, CAS signal, write command signal, and read command signal) and the address signal ADD_ 2 input through the second input/output port.
- command signals e.g., bank select signal CMD_A 2 , RAS signal, CAS signal, write command signal, and read command signal
- the address signal ADD_ 2 input through the second input/output port.
- the second data sense amplifier 310 is for read operation of data Dout_ 2 stored in the A bank 100 a and outputting data Dout_ 2
- the second data driver 320 is for write operation of external input data Din_ 2 and storing data Din_ 2 in the A bank 100 a.
- the select control unit 400 a includes a command multiplexer portion including a first command multiplexer 410 and a second command multiplexer 460 , a data multiplexer portion including a first data multiplexer 420 and a second data multiplexer 430 , and an address multiplexer portion including a row address multiplexer 440 and a column address multiplexer 450 .
- the command multiplexer portion 410 and 460 generates select control signals ICMD_ 1 and ICMD_ 2 for allocating the A bank 100 a as one of a first input/output port dedicated access area, a second input/output port dedicated access area, and a shared access area.
- the first command multiplexer 410 generates a first select control signal ICMD_ 1 for the first input/output port in response to an A bank select signal CMD_A 1 that is a command signal for selecting the A bank 100 a , and access path control command signals Fix_ 1 and Shared.
- the first select control signal ICMD_ 1 controls the access path to set the A bank 100 a as one of the first input/output port dedicated access area and the shared access area.
- the second command multiplexer 460 generates a second select control signal ICMD_ 2 for the second input/output port in response to an A bank select signal CMD_A 2 that is a command signal for selecting the A bank 100 a , and access path control command signals Fix_ 2 and Shared.
- the second select control signal ICMD_ 2 controls the access path to set the A bank 100 a as one of the second input/output port dedicated access area and the shared access area.
- the access path to a selected memory area is preferably determined by the access path control command signals Fix_ 1 , Fix_ 2 , and Shared.
- the command signal Fix_ 1 is for setting the A bank 100 a as the first input/output port dedicated access area
- the command signal Fix_ 2 is for setting the A bank 100 a as the second input/output port dedicated access area
- the command signal Shared is for setting the A bank 100 a as the shared access area that can be accessed at both the first and second input/output ports.
- an input/output port used to access the A bank 100 a is determined by applying one of the access path control command signals Fix_ 1 , Fix_ 2 , and Shared as logic ‘high’ and applying the remaining signals as logic ‘low’.
- one of the access path control command signals Fix 1 , Fix 2 , and Shared may be applied as logic ‘low’ and the remaining signals as logic ‘high’.
- the access path control command signals Fix_ 1 , Fix_ 2 , and Shared may be input through the first input/output port or the second input/output port. Further, command signals Fix_ 1 and Shared may be input through the first input/output port, and the command signal Fix_ 2 may be input through the second input/output port.
- the access path control command signals Fix_ 1 , Fix_ 2 , and Shared may be an MRS signal or a signal generated based on the MRS signal. Alternatively, they may be command signals generated by combining command signals normally used in the semiconductor memory device or by selecting any command signal.
- the data multiplexer portion 420 and 430 controls a data path between the first and second input/output port control units 200 a and 300 a and the A bank 100 a in response to the select control signals ICMD_ 1 and ICMD_ 2 .
- the first data multiplexer 420 controls a data path between the first port control unit 200 a and the A bank 100 a in response to the first select control signal ICMD_ 1 .
- the first select control signal ICMD_ 1 is generated in response to the access path control command signals Fix_ 1 and Shared
- the first data multiplexer 420 controls to electrically connect the data line DL of the A bank 100 a with the first data sense amplifier 210 or the first data driver 220 in the first port control unit 200 a . Accordingly, data input through the first input/output port may be stored in the memory cell of the A bank 100 a , and data stored in the A bank 100 a may be sensed and output through the first input/output port.
- the second data multiplexer 430 controls a data path between the second port control unit 300 a and the A bank 100 a in response to the second select control signal ICMD_ 2 .
- the second data multiplexer 430 controls to electrically connect the data line DL of the A bank 100 a with the second data sense amplifier 310 or the second data driver 320 in the second port control unit 300 a . Accordingly, data input through the second input/output port may be stored in the memory cell of the A bank 100 a , and data stored in the A bank 100 a may be sensed and output through the second input/output port.
- the address multiplexer portion 440 and 450 controls the address path between the first and second input/output port control units 200 a and 300 a and the A bank 100 a in response to the select control signals ICMD_ 1 and ICMD_ 2 .
- the row address multiplexer 440 controls a row address path between the first port control unit 200 a and the A bank 100 a in response to the first select control signal ICMD_ 1 , and controls a row address path between the second port control unit 300 a and the A bank 100 a in response to the second select control signal ICMD_ 2 .
- the row address multiplexer 440 delivers a row address signal ADD_ 1 input through the first input/output port to the row decoder 110 .
- the row address multiplexer 440 delivers a row address signal ADD_ 2 input through the second input/output port to the row decoder 110 . Accordingly, a word line WL connected with a specific memory cell in the A bank 100 a is selected and enabled.
- the column address multiplexer 450 controls a column address path between the first port control unit 200 a and the A bank 100 a in response to the first select control signal ICMD_ 1 , and controls a column address path between the second port control unit 300 a and the A bank 100 a in response to the second select control signal ICMD_ 2 .
- the column address multiplexer 450 delivers the column address signal ADD_ 1 input through the first input/output port to the column decoder 120 .
- the column address multiplexer 450 delivers the column address signal ADD_ 2 input through the second input/output port to the column decoder 110 . Accordingly, a bit line BL connected with a specific memory cell in the A bank 100 a is selected.
- the row address signal and the column address signal are not the same but indicated by the same reference numeral since they are included in typical address signals ADD_ 1 and ADD_ 2 .
- FIGS. 4 to 8 illustrate examples of components of the first port control unit 200 a and the select control unit 400 a in FIG. 3 .
- Components of the second port control unit 300 a may be similarly configured as the components of the first port control unit 200 a .
- a description of the components of the second port control unit 300 a is omitted.
- FIG. 4 illustrates an example of the first command multiplexer 410 of FIG. 3 .
- the second command multiplexer 460 of FIG. 3 may be similarly configured as the first command multiplexer 410 .
- the first command multiplexer 410 includes a logic OR circuit OR 410 , a logic NAND circuit NA 410 , and an inverter circuit IN 410 .
- the logic OR circuit OR 410 performs a logic operation on external access path control command signals Fix_ 1 and Shared and outputs a logic signal. For example, the logic OR circuit OR 410 outputs a logic ‘low’ signal when the access path command signals Fix_ 1 and Shared are both logic ‘low’, and outputs a logic ‘high’ signal when any one of the access path command signals Fix_ 1 and Shared is logic ‘high’.
- the logic NAND circuit NA 410 performs a logic operation on the output signal of the logic OR circuit OR 410 and an A bank select signal CMD_A 1 .
- the logic NAND circuit NA 410 outputs a logic ‘low’ signal when the output signal of the logic OR circuit OR 410 and the A bank select signal CMD_A 1 received through the first input/output port are both logic ‘high’, and outputs a logic ‘high’ signal, otherwise.
- the inverter circuit IN 410 then inverts the output signal of the NAND circuit NA 410 and outputs the first select control signal ICMD_ 1 .
- the A bank select signal CMD_A 1 contributing to generation of the first select control signal ICMD_ 1 and the A bank select signal CMD_A 2 contributing to generation of the second select control signal ICMD_ 2 are the same signal for selecting the A bank and are merely classified depending on an input/output port used to apply the signal. Accordingly, the A bank select signal CMD_A 1 and the A bank select signal CMD_A 2 cannot simultaneously have a logic ‘high’ level.
- FIG. 5 illustrates an example of the row address multiplexer 440 of FIG. 3 .
- the column address multiplexer 450 of FIG. 3 has a similar configuration as the row address multiplexer 440 except that the column address multiplexer 450 receives the column address signal instead of the row address signal and applies an output signal to the column decoder 120 . Accordingly, a description of the column address multiplexer 450 is omitted.
- the row address multiplexer 440 includes inverter circuits IN 440 , IN 442 , IN 444 , IN 446 , and IN 448 and transfer gates TG 440 and TG 442 .
- the transfer gate TG 440 operates when the first select control signal ICMD_ 1 is logic ‘high’ and the second select control signal ICMD_ 2 is logic ‘low’. Accordingly, an address signal ADD_ 1 received through the first input/output port control unit 200 a is transferred via the transfer gate TG 440 , latched in a latch circuit including inverters IN 442 and IN 446 , and then sent to the row decoder 110 .
- the other transfer gate TG 442 operates when the first select control signal ICMD_ 1 is logic ‘low’ and the second select control signal ICMD_ 2 is logic ‘high’. Accordingly, an address signal ADD_ 2 received through the second input/output port control unit 300 a is transferred via the transfer gate TG 442 , latched in a latch circuit including inverters IN 442 and IN 446 , and then sent to the row decoder 110 .
- the transfer gates TG 440 and TG 442 do not operate when the first select control signal ICMD_ 1 and the second select control signal ICMD_ 2 are both logic ‘low’. Accordingly, the address signal is not applied to the row decoder 110 .
- the first select control signal ICMD_ 1 and the second select control signal ICMD_ 2 cannot simultaneously be logic ‘high’. This is because the A bank select signal CMD_A 1 contributing to generation of the first select control signal ICMD_ 1 and the A bank select signal CMD_A 2 contributing to generation of the second select control signal ICMD_ 2 are set not to simultaneously be logic ‘high’.
- FIG. 6 illustrates an example of the first data sense amplifier 210 in the first port control unit 200 a of FIG. 3 .
- the second data sense amplifier 310 in the second port control unit 300 a may be similarly configured as the first data sense amplifier 210 .
- the first data sense amplifier 210 includes PMOS transistors P 210 and P 212 , NMOS transistors N 210 , N 212 and N 214 , an inverter IN 210 , and a NAND circuit NA 210 . Unlike a conventional sense amplifier circuit, the first data sense amplifier 210 includes the inverter IN 210 and the NAND circuit NA 210 . That is, the first data sense amplifier 210 senses and amplifies data DIO_ 1 and DIOB_ 1 read from the A bank 100 a . The first data sense amplifier 210 sends output data FDIO_ 1 and FDIOB_ 1 to a data output buffer (not shown) and/or an output driver (not shown) of the first port control unit 200 a.
- the first data sense amplifier 210 operates in response to a combination of the read command signal PREAD and the first select control signal ICMD_ 1 .
- the first data sense amplifier 210 may operate only when both the read command signal PREAD and the first select control signal ICMD_ 1 are logic ‘high’. This means that the first data sense amplifier 210 can operate in response to the first select control signal ICMD_ 1 only when the A bank is either the first input/output port dedicated access area or the shared access area.
- the first data sense amplifier as described above is applicable to all normally used data sense amplifiers. That is, the first data sense amplifier 210 can be implemented by a cross-coupled data sense amplifier, a current mirror type data sense amplifier, or the like.
- FIG. 7 illustrates an example of the first data driver 220 in the first port control unit 200 a of FIG. 3 .
- the second data driver 320 in the second port control unit 300 a may be similarly configured as the first data driver 320 .
- the first data driver 220 includes PMOS transistors P 220 and P 222 , NMOS transistors N 220 and N 222 , a logic NAND circuit NA 220 , and an inverter circuit IN 220 .
- the first data driver 220 drives and outputs the data Din_ 1 which is input through a data input buffer (not shown) in the first port control unit 200 a .
- Data DIO_ 1 output from the first data driver 220 is sent to the A bank 100 a via the first data multiplexer 420 .
- a write command signal PWRITE or its inverted signal is input to gates of the PMOS transistor P 220 and the NMOS transistor N 222 . Accordingly, the data driver operates only when the write command signal PWRITE (e.g., logic ‘high’) is applied.
- the first data driver 220 operates in response to a combination of the write command PWRITE and the first select control signal ICMD_ 1 . For example, the first data driver 220 may operate only when the write command signal PWRITE and the first select control signal ICMD_ 1 are both logic ‘high’.
- the first data driver 220 can operate in response to the first select control signal ICMD_ 1 only when the A bank is either the first input/output port dedicated access area or the shared access area. Thus, power consumption can be reduced and efficient operation can be achieved.
- the first data driver as described above is applicable to all normally used data drivers, and other data input circuits.
- FIG. 8 illustrates an example of the first data multiplexer 420 of FIG. 3 .
- the second data multiplexer 430 may be similarly configured as the first data multiplexer 420 .
- the first data multiplexer 420 includes an inverter IN 420 and PMOS transistors P 420 and P 422 .
- the first data multiplexer 420 controls data transmission of the A bank 100 a and the first port control unit 200 a through the PMOS transistors P 420 and P 422 responsive to an inverted version of the first select control signal ICMD_ 1 .
- data sensed from the A bank 100 a can be sent to the first port control unit 200 a only when the first select control signal ICMD_ 1 is logic ‘high’.
- data input via the first port control unit 200 a is sent to the A bank 100 a for the write operation only when the first select control signal ICMD_ 1 is logic ‘high’.
- FIGS. 3 to 8 are only examples provided for illustration purposes. It will be appreciated by those skilled in the art that other equivalent circuits or other variant circuits performing the operation illustrated in FIGS. 3 to 8 are included in the scope of the invention.
- FIGS. 9 to 15 illustrate examples of memory area allocation operations through variable access path control in the semiconductor memory device having the structure as described above according to an embodiment of the invention. These examples are provided for illustration purposes and should not be construed to limit the scope of the invention.
- the semiconductor memory device may include a plurality of input/output ports and a memory array divided into a plurality of memory areas.
- the semiconductor memory device is shown in FIGS. 9 to 15 as including a memory array 100 divided into four memory banks and two input/output ports.
- a B bank select signal corresponding to the A bank select signal CMD_A 1 applied through the first port control unit 200 is ‘CMD_B 1 ’ and a B bank select signal corresponding to the A bank select signal CMD_A 2 applied through the second port control unit 300 is ‘CMD_B 2 ’.
- a C bank select signal and a D bank select signal are ‘CMD_D 1 ’ and ‘CMD_D 2 ’.
- the access path control command signals Fix_ 1 , Fix_ 2 , and Shared have the same designation but are separate and independently applied signals for an access path to each memory bank.
- the access path control command signals Fix_ 1 , Fix_ 2 , and Shared as shown in FIGS. 3 to 8 are for the access path to the A bank 100 a and do not affect access paths to remaining banks.
- FIG. 9 illustrates an example in which the A bank 100 a and the B bank 100 b are allocated as the first input/output port dedicated access area, and the C bank 100 c and the D bank 100 d are allocated as the second input/output port dedicated access area.
- an access path PA 1 may be established between the A bank 100 a and the first port control unit 200 . That is, an A bank select signal CMD_A 1 and the access path control command signal Fix_ 1 generated only for the A bank 100 a may be enabled. For example, as described in FIGS. 3 to 8 , when the A bank select signal CMD_A 1 is applied at a logic ‘high’ level and when the signal Fix_ 1 is applied at a logic ‘high’ level, the A bank 100 a is allocated as the first input/output port dedicated access area.
- the command signals CMD_A 2 , Fix_ 2 and Shared remain at logic ‘low’ level.
- an access path PA 2 may be established between the B bank 100 b and the first port control unit 200 . That is, a B bank select signal CMD_B 1 and the access path control command signal Fix_ 1 generated only for the B bank 100 b may be enabled. For example, as in the A bank 100 a , when the B bank select signal CMD_B 1 is applied at a logic ‘high’ level and when the signal Fix_ 1 is applied at a logic ‘high’ level, the B bank 100 b is allocated as the first input/output port dedicated access area.
- the command signals CMD_B 2 , Fix_ 2 and Shared remain at logic ‘low’ level.
- an access path PA 3 may be established between the C bank 100 c and the second port control unit 300 . That is, a C bank select signal CMD_C 2 and the access path control command signal Fix_ 2 generated only for the C bank 100 c may be enabled. For example, as in the A bank 100 a , when the C bank select signal CMDL_C 2 is applied at a logic ‘high’ level and when the signal Fix_ 2 generated only for the C bank 100 c is applied at a logic ‘high’ level, the C bank 100 c is allocated as the second input/output port dedicated access area.
- the command signals CMD_C 1 , Fix_ 1 and Shared remain at logic ‘low’ level.
- an access path PA 4 may be established between the D bank 100 d and the second port control unit 300 . That is, when the D bank select signal CMD_D 2 is applied at a logic ‘high’ level and when the signal Fix_ 2 generated only for the D bank 100 d is applied at a logic ‘high’ level, the D bank 100 d is allocated as the second input/output port dedicated access area.
- the command signals CMD_D 1 , Fix_ 1 and Shared remain at logic ‘low’ level.
- FIG. 10 illustrates an operation example in which the A bank 100 a is allocated as the first input/output port dedicated access area, and the B bank 100 b , the C bank 100 c , and the D bank 100 d are allocated as the second input/output port dedicated access area.
- an access path PA 1 may be established between the A bank 100 a and the first port control unit 200 as previously described with reference to FIG. 9 .
- an access path PA 5 may be established between the B bank 100 b and the second port control unit 300 . That is, a B bank select signal CMD_B 2 and the access path control command signal Fix_ 2 generated only for the B bank 100 b may be enabled. For example, when the B bank select signal CMD_B 2 is applied at a logic ‘high’ level and when the signal Fix_ 2 for allocating the B bank 100 b as the second input/output port dedicated access area is applied at a logic ‘high’ level, the B bank 100 b is allocated as the second input/output port dedicated access area.
- the command signals CMD_B 1 , Fix_ 1 and Shared remain at logic ‘low’ level.
- access paths PA 3 and PA 4 may be established as previously described with reference to FIG. 9 .
- FIG. 11 shows an operation example in which the A bank 100 a , the B bank 100 b , the C bank 100 c , and the D bank 100 d are all allocated as the first input/output port dedicated access area.
- the multi-port semiconductor memory device can operate as a single port semiconductor memory device.
- access paths PA 1 , PA 2 , PA 7 , and PA 8 may be established between the respective memory banks 100 a , 100 b , 100 c and 100 d and the first port control unit 200 .
- An allocation operation example of setting the A bank 100 a and the B bank 100 b as the first input/output port dedicated areas has been described in FIG. 9 and, thus, a description thereof is omitted.
- an access path PA 7 may be established between the C bank 100 c and the first port control unit 200 .
- the C bank select signal CMD_C 1 is applied at a logic ‘high’ level and when the signal Fix_ 1 for allocating the C bank 100 c as the first input/output port dedicated access area is applied at a logic ‘high’ level, the C bank 100 c is allocated as the first input/output port dedicated access area.
- the command signals CMD_C 2 , Fix_ 2 and Shared remain at logic ‘low’ level.
- an access path PA 8 may be established between the D bank 100 d and the first port control unit 200 .
- the D bank select signal CMD_D 1 is applied at a logic ‘high’ level and when the signal Fix_ 1 for allocating the D bank 100 d as the first input/output port dedicated access area is applied at a logic ‘high’ level, the D bank 100 d is allocated as the first input/output port dedicated access area.
- the command signals CMD_C 2 , Fix_ 2 and Shared remain at logic ‘low’ level.
- FIG. 12 shows an operation example in which the A bank 100 a , the B bank 100 b , the C bank 100 c , and the D bank 100 d are all allocated as the second input/output port dedicated access area.
- this multi-port semiconductor memory device can operate as a single port semiconductor memory device.
- access paths PA 3 , PA 4 , PA 5 , and PA 6 may be established between the respective memory banks 100 a , 100 b , 100 c and 100 d and the second port control unit 300 .
- the allocation operation is similar to the operation described in FIG. 11 and need not be described in further detail.
- FIG. 13 illustrates an operation example in which the A bank 100 a is allocated as the first input/output port dedicated access area, the B bank 100 b as the shared access area, and the C bank 100 c and the D bank 100 d as the second input/output port dedicated access area.
- This case corresponds to a case in which there is the shared access area which can be accessed at both the first and second input/output ports.
- An access path PA 1 may be established in order to allocate the A bank 100 a as the first input/output port dedicated access area. Further, access paths PA 3 and PA 4 may be established between the respective C bank 100 c and the D bank 100 d and the second port control unit 300 in order to allocate the C bank 100 c and the D bank 100 d as the second input/output port dedicated access area. These allocation operations have been previously described in FIGS. 9 to 12 and need not be described in further detail.
- the access path PA 2 with the first port control unit 200 and the access path PA 5 with the second port control unit 300 may be established.
- the signal Shared for allocating the B bank 100 b as the shared access area may first be applied at a logic ‘high’ level.
- an access operation may be performed through a desired one of the access path PA 2 with the first port control unit 200 and the access path PA 5 with the second port control unit 300 .
- the B bank select signal CMD_B 1 may be applied at a logic ‘high’ level through the first port control unit in order to access the B bank 100 b through the first input/output port.
- the B bank select signal CMD_B 2 may then be applied at a logic ‘high’ level through the second port control unit in order to access the B bank 100 b through the second input/output port.
- the access path may be determined depending on an input/output port used to apply the B bank select signal CMD_B 1 or CMD_B 2 at a logic ‘high’ level.
- the signal Shared for allocating the B bank 100 b as the shared access area is applied at a logic ‘high’ level
- the first select control signal and the second select control signal for controlling the access paths PA 2 and PA 5 do not become a logic ‘high’ level. This provides an advantage of preventing collision between the input/output ports in the shared access area.
- the order of applying the command signals Shared, CMD_B 1 and CMD_B 2 can be changed.
- FIG. 14 illustrates an operation example in which the A bank 100 a and the B bank 100 b are allocated as the shared access area, and the C bank 100 c and the D bank 100 d as the second input/output port dedicated access area.
- the shared access area that can be accessed at both the first and second input/output ports includes two memory banks.
- access paths PA 3 and PA 4 may be established between the C bank 100 c and the D bank 100 d and the second port control unit 300 as previously described in FIGS. 9 to 13 . Further, an operation of allocating the B bank 100 b as the shared access area has been described in FIG. 13 and, thus, a description thereof is omitted.
- the access path PA 1 with the first port control unit 200 and the access path PA 6 with the second port control unit 300 may be established.
- the signal Shared for allocating the A bank 100 a as the shared access area may first be applied at a logic ‘high’ level.
- an access operation may be performed through a desired one of the access path PA 1 with the first port control unit 200 and the access path PA 6 with the second port control unit 300 .
- the A bank select signal CMD_A 1 may be applied at a logic ‘high’ level through the first port control unit 200 in order to access the A bank 100 a through the first input/output port.
- the A bank select signal CMD_A 2 may be applied at a logic ‘high’ level through the second port control unit in order to access the A bank 100 a through the second input/output port.
- the access path may be determined depending on an input/output port used to apply the A bank select signal CMD_A 1 or CMD_B 2 at a logic ‘high’ level. This provides an advantage of preventing collision between the input/output ports in the shared access area.
- the order of applying the command signals Shared, CMD_A 1 and CMD_A 2 can be changed.
- FIG. 15 illustrates an operation example in which all memory banks 100 a , 100 b , 100 c and 100 d are allocated as the shared access area.
- access paths PA 1 , PA 2 , PA 5 and PA 6 may be established to allocate the A bank 100 a and the B bank 100 b as the shared access area as previously described in FIGS. 13 and 14 .
- the access path PA 7 with the first port control unit 200 and the access path PA 3 with the second port control unit 300 may be established.
- the signal Shared for allocating the C bank 100 c as the shared access area may first be applied at a logic ‘high’ level.
- an access operation may be performed through a desired one of the access path PA 7 with the first port control unit 200 and the access path PA 3 with the second port control unit 300 .
- the C bank select signal CMD_C 1 is applied at a logic ‘high’ level through the first port control unit 200 in order to access the C bank 100 c through the first input/output port.
- the C bank select signal CMD_C 2 is applied at a logic ‘high’ level through the second port control unit in order to access the C bank 100 c through the second input/output port. In the C bank 100 c , access collision is prevented between the input/output ports.
- the order of applying the command signals Shared, CMD_C 1 and CMD_C 2 can be changed.
- the access path PA 8 with the first port control unit 200 and the access path PA 4 with the second port control unit 300 may be established.
- the signal Shared for allocating the D bank 100 d as the shared access area is first applied at a logic ‘high’ level.
- an access operation may be performed through a desired one of the access path PA 8 with the first port control unit 200 and the access path PA 4 with the second port control unit 300 .
- the D bank select signal CMD_D 1 is applied at a logic ‘high’ level through the first port control unit 200 in order to access the D bank 100 d through the first input/output port.
- the D bank select signal CMD_D 2 is applied at a logic ‘high’ level through the second port control unit in order to access the D bank 100 d through the second input/output port. In the D bank 100 d , access collision is prevented between the input/output ports, as well.
- the order of applying the command signals Shared, CMD_D 1 and CMD_D 2 can be changed.
- the semiconductor memory device as described above according to an embodiment of the invention is also useful for testing. That is, the semiconductor memory device has an advantage when performing a test according to conditions by controlling the access paths in a given test environment.
- all of the memory banks 100 a , 100 b , 100 c and 100 d may be allocated as the first input/output port dedicated access area as in FIG. 11 or the second input/output port dedicated access area as in FIG. 12 . Then, the test may be performed through the first input/output port or the second input/output port. Accordingly, the number of the test pins can be reduced. In this case, other memory devices may be tested using remaining test pins.
- the memory banks 100 a , 100 b , 100 c and 100 d may be divided into two groups and allocated as the first input/output port dedicated access area and the second input/output port dedicated access area, as in FIG. 9 . Then, testing may be performed through the first input/output port or the second input/output port. Accordingly, the test time can be reduced.
- control of the access paths for the test operation may be performed through the operation as described in FIGS. 2 to 15 .
- the external command signal may be an external command signal for test (e.g., MRS signal for test) or a combination of other input command signals.
- the access paths used to access the memory areas constituting the multi-port semiconductor memory device through the respective input/output ports may be variably controlled.
- the memory areas can be efficiently utilized by a user.
- the test according to a test environment is possible and, thus, efficient testing can be performed.
Abstract
A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
Description
- The above-referenced application is a Continuation of U.S. Ser. No. 11/466,389, filed on Aug. 22, 2006, now pending, which claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 2005-127534, filed Dec. 22, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety.
- 1. Technical Field
- The invention relates to multi-port semiconductor memory devices having variable access paths and, more particularly, to a semiconductor memory device and a method for performing a normal operation or a test operation by variably controlling access paths between a plurality of input/output ports and a plurality of memory areas.
- 2. Discussion of Related Art
- In general, semiconductor memory devices such as random access memories (RAMs) include one port having a number of input/output pin sets in order to communicate with an external processor.
-
FIG. 1 illustrates a conventional semiconductor memory device having four memory banks and a single input/output port. The conventional semiconductor memory device includes amemory array 10 having fourmemory banks port control unit 20 for controlling a single input/output port. Theport control unit 20 includes control circuits for controlling a command signal, an address signal, a data signal, and other signals input or output through the input/output port. All of thememory banks port control unit 20. The arrows indicate the access paths. - The conventional semiconductor memory device having a single input/output port has problems with access speed and access efficiency. For example, to perform a first operation of storing first data in the
A bank 10 a and a second operation of reading second data from the B bank, which is distinct from the first operation, the semiconductor memory device must perform the operations sequentially, the first operation and then the second operation or vice versa. This is not suitable for high speed and high efficiency. - For higher speed and greater efficiency, a multi-port semiconductor memory device that performs communication through a plurality of processors and has memory cells that can be accessed through a plurality of input/output ports has been developed. An example of such a conventional multi-port semiconductor memory device is disclosed in U.S. Pat. No. 5,815,456, Sep. 29, 1998.
- Generally, the conventional multi-port semiconductor memory device may have several structures to enable accessing of memory cells. Three representative structures include: (1) a structure allowing all memory cells to be accessed through any of a plurality of input/output ports; (2) a structure allowing each memory cell to be accessed only through fixed input/output ports; and (3) a structure allowing specific memory cells to be accessed only through fixed input/output ports and any remaining memory cells to be accessed through any ports.
- In these structures, because access paths between the input/output ports and the memory cells are prescribed in hardware, a change among the structures is impossible. That is, a user is not allowed to change, for example, (1) the structure allowing all memory cells to be accessed through any of a plurality of input/output ports, into (2) the structure allowing each memory cell to be accessed only through fixed input/output ports. This inflexibility degrades operational efficiency of the multi-port semiconductor memory device. In addition, since a test should be separately performed through each input/output port, this inflexibility also degrades test efficiency.
- One aspect of the invention is a semiconductor memory device having a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to establish variable access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
- Another aspect of the invention is, in a semiconductor memory device comprising a plurality of input/output ports and a memory array divided into a plurality of memory areas, a method for variably accessing the memory areas includes allocating the memory areas for access through at least one of the input/output ports and establishing data and address paths between the memory areas and corresponding input/output ports according to the memory area allocation. The method further includes re-applying the external command signals to re-allocate the memory areas for access through different input/output ports and establishing new data and address paths between the memory areas and the different input/output ports according to the memory area re-allocation.
- Yet another aspect of the invention provides a method for testing a multi-port semiconductor memory device comprising a plurality of input/output ports and a memory array divided into a plurality of memory areas, the method including: allocating the memory areas to each input/output port, so that each memory area is accessed through at least one of the input/output ports; and testing the allocated memory areas through each corresponding input/output port. The method for testing may further include re-allocating the memory areas, so that each memory area is access through different input/output ports; and testing the re-allocated memory areas through the corresponding different input/output ports.
- The above and other features and advantages of embodiments of the invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings in which:
-
FIG. 1 illustrates access paths of a conventional semiconductor memory device having four memory banks and a single input/output port; -
FIG. 2 is a schematic block diagram illustrating a multi-port semiconductor memory device according to an embodiment of the invention; -
FIG. 3 is a block diagram illustrating a select control unit 400 a and first and secondport control units FIG. 2 ; -
FIG. 4 is a circuit diagram of a first command multiplexer ofFIG. 3 ; -
FIG. 5 is a circuit diagram illustrating a row address multiplexer ofFIG. 3 ; -
FIG. 6 is a circuit diagram illustrating a first data sense amplifier ofFIG. 3 ; -
FIG. 7 is a circuit diagram illustrating a first data driver ofFIG. 3 ; -
FIG. 8 is a circuit diagram illustrating a first data multiplexer ofFIG. 3 ; and -
FIGS. 9 to 15 illustrate an example of an access path control operation in a semiconductor memory device according to an embodiment of the invention. - As will be apparent to those skilled in the art from the following disclosure, the invention as described herein may be embodied in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will fully convey the principles of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.
- For convenience of understanding, a multi-port semiconductor memory device having two input/output ports will be described. However, it will be appreciated by those skilled in the art that the invention may be applied to a multi-port semiconductor memory device having two or more input/output ports.
-
FIG. 2 is a schematic block diagram illustrating a multi-port semiconductor memory device according to an embodiment of the invention. The multi-port semiconductor memory device includes amemory array 100, a firstport control unit 200 for controlling signals input or output through a first input/output port, a secondport control unit 300 for controlling signals input or output through a second input/output port different from the first input/output port, and aselect control unit 400. - The
memory array 100 is divided into a plurality of different memory areas. For example, the memory array may be divided into fourmemory banks - It is to be understood that the first
port control unit 200 and the secondport control unit 300 include the first input/output port and the second input/output port, respectively. The firstport control unit 200 includes control circuits for controlling a command signal, an address signal, a data signal, and other signals input or output through the first input/output port. Similarly, the secondport control unit 300 includes control circuits for controlling a command signal, an address signal, a data signal, and other signals input or output through the second input/output port. - The
select control unit 400 performs a memory allocation operation that controls a data path and an address path between the input/output ports and the memory areas constituting thememory array 100. That is, theselect control unit 400 preferably controls access paths between the memory areas and the input/output ports so that each memory area may be variably accessed through at least one of the input/output ports. For example, theselect control unit 400 controls the access path to variably allocate each of the fourmemory banks - The
select control unit 400 may perform a memory allocation operation in response to a mode register set (MRS) signal for a normal operation and in response to an MRS signal for a test operation. Theselect control unit 400 may also operate in response to a command signal generated by any external command signals normally applied for operation of the semiconductor memory device or a combination of the external command signals, which are not the MRS signal. The external command signals may be separate, independent signals that each correspond to the memory areas. -
FIG. 3 is a block diagram illustrating an example of a select control unit 400 a and first and secondport control units bank 100 a) to the first or second input/output port inFIG. 2 . A select control unit 400 a and first and secondport control units FIG. 3 are for only one memory bank (e.g., Abank 100 a). Accordingly, as will be appreciated by those skilled in the art, if the semiconductor memory device has a plurality of memory banks, a select control unit and port control units for each memory bank may be similarly configured as the select control unit 400 a and the first and secondport control units - The
A bank 100 a in thememory array 100 ofFIGS. 2 and 3 may refer to one of a plurality of memory banks in a typical semiconductor memory device. TheA bank 100 a may also refer to an internal sub block constituting a memory bank, which is a smaller unit than a typical memory bank. TheA bank 100 a may also refer to a combination of two or more memory banks. - Each memory cell in the
A bank 100 is selected by one of word lines WL and one of bit lines BL. Arow decoder 110 for selecting the word line WL in theA bank 100 a and acolumn decoder 120 for selecting the bit line BL in theA bank 100 a are provided around theA bank 100 a. - The first
port control unit 200 a includes a firstdata sense amplifier 210 and afirst data driver 220 for controlling data input to or output from the A bank through the first input/output port. The firstport control unit 200 a may additionally include a data buffer circuit or a latch circuit for controlling data input and output. The firstport control unit 200 a may further include control circuits (e.g., command buffer circuit, command latch circuit, address latch circuit, and address buffer circuit) for controlling command signals (e.g., bank select signal CMD_A1, RAS signal, CAS signal, write command signal, and read command signal) and the address signal ADD_1 input through the first input/output port. Here, the firstdata sense amplifier 210 is for read operation of data Dout_1 stored in theA bank 100 a and outputting data Dout_1, and thefirst data driver 220 is for write operation of external input data Din_1 and storing data Din_1 in theA bank 100 a. - The second
port control unit 300 a includes a seconddata sense amplifier 310 and asecond data driver 320 for controlling data input to or output from the A bank through the second input/output port. The secondport control unit 300 a may additionally include a data buffer circuit or a latch circuit for controlling data input and output. The secondport control unit 300 a may further include control circuits (e.g., command buffer circuit, command latch circuit, address latch circuit, and address buffer circuit) for controlling command signals (e.g., bank select signal CMD_A2, RAS signal, CAS signal, write command signal, and read command signal) and the address signal ADD_2 input through the second input/output port. Here, the seconddata sense amplifier 310 is for read operation of data Dout_2 stored in theA bank 100 a and outputting data Dout_2, and thesecond data driver 320 is for write operation of external input data Din_2 and storing data Din_2 in theA bank 100 a. - The select control unit 400 a includes a command multiplexer portion including a
first command multiplexer 410 and asecond command multiplexer 460, a data multiplexer portion including afirst data multiplexer 420 and asecond data multiplexer 430, and an address multiplexer portion including arow address multiplexer 440 and acolumn address multiplexer 450. - The
command multiplexer portion A bank 100 a as one of a first input/output port dedicated access area, a second input/output port dedicated access area, and a shared access area. Thefirst command multiplexer 410 generates a first select control signal ICMD_1 for the first input/output port in response to an A bank select signal CMD_A1 that is a command signal for selecting theA bank 100 a, and access path control command signals Fix_1 and Shared. The first select control signal ICMD_1 controls the access path to set theA bank 100 a as one of the first input/output port dedicated access area and the shared access area. - The
second command multiplexer 460 generates a second select control signal ICMD_2 for the second input/output port in response to an A bank select signal CMD_A2 that is a command signal for selecting theA bank 100 a, and access path control command signals Fix_2 and Shared. The second select control signal ICMD_2 controls the access path to set theA bank 100 a as one of the second input/output port dedicated access area and the shared access area. - The access path to a selected memory area (e.g., the
A bank 100 a) is preferably determined by the access path control command signals Fix_1, Fix_2, and Shared. The command signal Fix_1 is for setting theA bank 100 a as the first input/output port dedicated access area, the command signal Fix_2 is for setting theA bank 100 a as the second input/output port dedicated access area, and the command signal Shared is for setting theA bank 100 a as the shared access area that can be accessed at both the first and second input/output ports. For example, an input/output port used to access theA bank 100 a is determined by applying one of the access path control command signals Fix_1, Fix_2, and Shared as logic ‘high’ and applying the remaining signals as logic ‘low’. Of course, one of the access path control command signals Fix1, Fix2, and Shared may be applied as logic ‘low’ and the remaining signals as logic ‘high’. - The access path control command signals Fix_1, Fix_2, and Shared may be input through the first input/output port or the second input/output port. Further, command signals Fix_1 and Shared may be input through the first input/output port, and the command signal Fix_2 may be input through the second input/output port.
- The access path control command signals Fix_1, Fix_2, and Shared may be an MRS signal or a signal generated based on the MRS signal. Alternatively, they may be command signals generated by combining command signals normally used in the semiconductor memory device or by selecting any command signal.
- The
data multiplexer portion port control units A bank 100 a in response to the select control signals ICMD_1 and ICMD_2. Thefirst data multiplexer 420 controls a data path between the firstport control unit 200 a and theA bank 100 a in response to the first select control signal ICMD_1. For example, if the first select control signal ICMD_1 is generated in response to the access path control command signals Fix_1 and Shared, thefirst data multiplexer 420 controls to electrically connect the data line DL of theA bank 100 a with the firstdata sense amplifier 210 or thefirst data driver 220 in the firstport control unit 200 a. Accordingly, data input through the first input/output port may be stored in the memory cell of theA bank 100 a, and data stored in theA bank 100 a may be sensed and output through the first input/output port. - The
second data multiplexer 430 controls a data path between the secondport control unit 300 a and theA bank 100 a in response to the second select control signal ICMD_2. For example, if the second select control signal ICMD_2 is generated in response to the access path control command signals Fix_2 and Shared, thesecond data multiplexer 430 controls to electrically connect the data line DL of theA bank 100 a with the seconddata sense amplifier 310 or thesecond data driver 320 in the secondport control unit 300 a. Accordingly, data input through the second input/output port may be stored in the memory cell of theA bank 100 a, and data stored in theA bank 100 a may be sensed and output through the second input/output port. - The
address multiplexer portion port control units A bank 100 a in response to the select control signals ICMD_1 and ICMD_2. Therow address multiplexer 440 controls a row address path between the firstport control unit 200 a and theA bank 100 a in response to the first select control signal ICMD_1, and controls a row address path between the secondport control unit 300 a and theA bank 100 a in response to the second select control signal ICMD_2. For example, when the first select control signal ICMD_1 is generated in response to the access path control command signals Fix_1 and Shared, therow address multiplexer 440 delivers a row address signal ADD_1 input through the first input/output port to therow decoder 110. When the second select control signal ICMD_2 is generated in response to the access path control command signals Fix_2 and Shared, therow address multiplexer 440 delivers a row address signal ADD_2 input through the second input/output port to therow decoder 110. Accordingly, a word line WL connected with a specific memory cell in theA bank 100 a is selected and enabled. - The
column address multiplexer 450 controls a column address path between the firstport control unit 200 a and theA bank 100 a in response to the first select control signal ICMD_1, and controls a column address path between the secondport control unit 300 a and theA bank 100 a in response to the second select control signal ICMD_2. For example, when the first select control signal ICMD_1 is generated in response to the access path control command signals Fix_1 and Shared, thecolumn address multiplexer 450 delivers the column address signal ADD_1 input through the first input/output port to thecolumn decoder 120. When the second select control signal ICMD_2 is generated in response to the access path control command signals Fix_2 and Shared, thecolumn address multiplexer 450 delivers the column address signal ADD_2 input through the second input/output port to thecolumn decoder 110. Accordingly, a bit line BL connected with a specific memory cell in theA bank 100 a is selected. Here, the row address signal and the column address signal are not the same but indicated by the same reference numeral since they are included in typical address signals ADD_1 and ADD_2. -
FIGS. 4 to 8 illustrate examples of components of the firstport control unit 200 a and the select control unit 400 a inFIG. 3 . Components of the secondport control unit 300 a may be similarly configured as the components of the firstport control unit 200 a. Thus, a description of the components of the secondport control unit 300 a is omitted. -
FIG. 4 illustrates an example of thefirst command multiplexer 410 ofFIG. 3 . Thesecond command multiplexer 460 ofFIG. 3 may be similarly configured as thefirst command multiplexer 410. - The
first command multiplexer 410 includes a logic OR circuit OR410, a logic NAND circuit NA410, and an inverter circuit IN410. The logic OR circuit OR410 performs a logic operation on external access path control command signals Fix_1 and Shared and outputs a logic signal. For example, the logic OR circuit OR410 outputs a logic ‘low’ signal when the access path command signals Fix_1 and Shared are both logic ‘low’, and outputs a logic ‘high’ signal when any one of the access path command signals Fix_1 and Shared is logic ‘high’. - The logic NAND circuit NA410 performs a logic operation on the output signal of the logic OR circuit OR410 and an A bank select signal CMD_A1. The logic NAND circuit NA410 outputs a logic ‘low’ signal when the output signal of the logic OR circuit OR410 and the A bank select signal CMD_A1 received through the first input/output port are both logic ‘high’, and outputs a logic ‘high’ signal, otherwise. The inverter circuit IN410 then inverts the output signal of the NAND circuit NA410 and outputs the first select control signal ICMD_1.
- Referring back to
FIG. 3 , the A bank select signal CMD_A1 contributing to generation of the first select control signal ICMD_1 and the A bank select signal CMD_A2 contributing to generation of the second select control signal ICMD_2 are the same signal for selecting the A bank and are merely classified depending on an input/output port used to apply the signal. Accordingly, the A bank select signal CMD_A1 and the A bank select signal CMD_A2 cannot simultaneously have a logic ‘high’ level. -
FIG. 5 illustrates an example of therow address multiplexer 440 ofFIG. 3 . Thecolumn address multiplexer 450 ofFIG. 3 has a similar configuration as therow address multiplexer 440 except that thecolumn address multiplexer 450 receives the column address signal instead of the row address signal and applies an output signal to thecolumn decoder 120. Accordingly, a description of thecolumn address multiplexer 450 is omitted. - The
row address multiplexer 440 includes inverter circuits IN440, IN442, IN444, IN446, and IN448 and transfer gates TG440 and TG442. The transfer gate TG440 operates when the first select control signal ICMD_1 is logic ‘high’ and the second select control signal ICMD_2 is logic ‘low’. Accordingly, an address signal ADD_1 received through the first input/outputport control unit 200 a is transferred via the transfer gate TG440, latched in a latch circuit including inverters IN442 and IN446, and then sent to therow decoder 110. The other transfer gate TG442 operates when the first select control signal ICMD_1 is logic ‘low’ and the second select control signal ICMD_2 is logic ‘high’. Accordingly, an address signal ADD_2 received through the second input/outputport control unit 300 a is transferred via the transfer gate TG442, latched in a latch circuit including inverters IN442 and IN446, and then sent to therow decoder 110. The transfer gates TG440 and TG442 do not operate when the first select control signal ICMD_1 and the second select control signal ICMD_2 are both logic ‘low’. Accordingly, the address signal is not applied to therow decoder 110. - The first select control signal ICMD_1 and the second select control signal ICMD_2 cannot simultaneously be logic ‘high’. This is because the A bank select signal CMD_A1 contributing to generation of the first select control signal ICMD_1 and the A bank select signal CMD_A2 contributing to generation of the second select control signal ICMD_2 are set not to simultaneously be logic ‘high’.
-
FIG. 6 illustrates an example of the firstdata sense amplifier 210 in the firstport control unit 200 a ofFIG. 3 . The seconddata sense amplifier 310 in the secondport control unit 300 a may be similarly configured as the firstdata sense amplifier 210. - The first
data sense amplifier 210 includes PMOS transistors P210 and P212, NMOS transistors N210, N212 and N214, an inverter IN210, and a NAND circuit NA210. Unlike a conventional sense amplifier circuit, the firstdata sense amplifier 210 includes the inverter IN210 and the NAND circuit NA210. That is, the firstdata sense amplifier 210 senses and amplifies data DIO_1 and DIOB_1 read from theA bank 100 a. The firstdata sense amplifier 210 sends output data FDIO_1 and FDIOB_1 to a data output buffer (not shown) and/or an output driver (not shown) of the firstport control unit 200 a. - While the conventional data sense amplifier operates in response to an applied read command signal PREAD because the read command signal PREAD is input to a gate of an NMOS transistor N214, the first
data sense amplifier 210 operates in response to a combination of the read command signal PREAD and the first select control signal ICMD_1. For example, the firstdata sense amplifier 210 may operate only when both the read command signal PREAD and the first select control signal ICMD_1 are logic ‘high’. This means that the firstdata sense amplifier 210 can operate in response to the first select control signal ICMD_1 only when the A bank is either the first input/output port dedicated access area or the shared access area. Thus, power consumption can be reduced and efficient operation can be achieved. The first data sense amplifier as described above is applicable to all normally used data sense amplifiers. That is, the firstdata sense amplifier 210 can be implemented by a cross-coupled data sense amplifier, a current mirror type data sense amplifier, or the like. -
FIG. 7 illustrates an example of thefirst data driver 220 in the firstport control unit 200 a ofFIG. 3 . Thesecond data driver 320 in the secondport control unit 300 a may be similarly configured as thefirst data driver 320. - The
first data driver 220 includes PMOS transistors P220 and P222, NMOS transistors N220 and N222, a logic NAND circuit NA220, and an inverter circuit IN220. For a write operation, thefirst data driver 220 drives and outputs the data Din_1 which is input through a data input buffer (not shown) in the firstport control unit 200 a. Data DIO_1 output from thefirst data driver 220 is sent to theA bank 100 a via thefirst data multiplexer 420. - In the conventional data driver circuit, a write command signal PWRITE or its inverted signal is input to gates of the PMOS transistor P220 and the NMOS transistor N222. Accordingly, the data driver operates only when the write command signal PWRITE (e.g., logic ‘high’) is applied. Unlike the conventional data driver circuit, the
first data driver 220 operates in response to a combination of the write command PWRITE and the first select control signal ICMD_1. For example, thefirst data driver 220 may operate only when the write command signal PWRITE and the first select control signal ICMD_1 are both logic ‘high’. This means that thefirst data driver 220 can operate in response to the first select control signal ICMD_1 only when the A bank is either the first input/output port dedicated access area or the shared access area. Thus, power consumption can be reduced and efficient operation can be achieved. The first data driver as described above is applicable to all normally used data drivers, and other data input circuits. -
FIG. 8 illustrates an example of thefirst data multiplexer 420 ofFIG. 3 . Thesecond data multiplexer 430 may be similarly configured as thefirst data multiplexer 420. Thefirst data multiplexer 420 includes an inverter IN420 and PMOS transistors P420 and P422. - The
first data multiplexer 420 controls data transmission of theA bank 100 a and the firstport control unit 200 a through the PMOS transistors P420 and P422 responsive to an inverted version of the first select control signal ICMD_1. For example, data sensed from theA bank 100 a can be sent to the firstport control unit 200 a only when the first select control signal ICMD_1 is logic ‘high’. Further, data input via the firstport control unit 200 a is sent to theA bank 100 a for the write operation only when the first select control signal ICMD_1 is logic ‘high’. - The circuits illustrated in
FIGS. 3 to 8 are only examples provided for illustration purposes. It will be appreciated by those skilled in the art that other equivalent circuits or other variant circuits performing the operation illustrated inFIGS. 3 to 8 are included in the scope of the invention. -
FIGS. 9 to 15 illustrate examples of memory area allocation operations through variable access path control in the semiconductor memory device having the structure as described above according to an embodiment of the invention. These examples are provided for illustration purposes and should not be construed to limit the scope of the invention. - The semiconductor memory device according to the invention may include a plurality of input/output ports and a memory array divided into a plurality of memory areas. For convenience of understanding, however, the semiconductor memory device is shown in
FIGS. 9 to 15 as including amemory array 100 divided into four memory banks and two input/output ports. - While the embodiments have been described in connection with the
A bank 100 a, it will be appreciated by those skilled in the art that the configuration as described above can be obtained in connection with other memory banks. It is assumed that a B bank select signal corresponding to the A bank select signal CMD_A1 applied through the firstport control unit 200 is ‘CMD_B1’ and a B bank select signal corresponding to the A bank select signal CMD_A2 applied through the secondport control unit 300 is ‘CMD_B2’. In this manner, it may be assumed that a C bank select signal and a D bank select signal are ‘CMD_D1’ and ‘CMD_D2’. - As previously described, the access path control command signals Fix_1, Fix_2, and Shared have the same designation but are separate and independently applied signals for an access path to each memory bank. For example, the access path control command signals Fix_1, Fix_2, and Shared as shown in
FIGS. 3 to 8 are for the access path to theA bank 100 a and do not affect access paths to remaining banks. -
FIG. 9 illustrates an example in which theA bank 100 a and theB bank 100 b are allocated as the first input/output port dedicated access area, and theC bank 100 c and theD bank 100 d are allocated as the second input/output port dedicated access area. - To allocate the
A bank 100 a as the first input/output port dedicated access area, an access path PA1 may be established between theA bank 100 a and the firstport control unit 200. That is, an A bank select signal CMD_A1 and the access path control command signal Fix_1 generated only for theA bank 100 a may be enabled. For example, as described inFIGS. 3 to 8 , when the A bank select signal CMD_A1 is applied at a logic ‘high’ level and when the signal Fix_1 is applied at a logic ‘high’ level, theA bank 100 a is allocated as the first input/output port dedicated access area. The command signals CMD_A2, Fix_2 and Shared remain at logic ‘low’ level. - To allocate the
B bank 100 b as the first input/output port dedicated access area, an access path PA2 may be established between theB bank 100 b and the firstport control unit 200. That is, a B bank select signal CMD_B1 and the access path control command signal Fix_1 generated only for theB bank 100 b may be enabled. For example, as in theA bank 100 a, when the B bank select signal CMD_B1 is applied at a logic ‘high’ level and when the signal Fix_1 is applied at a logic ‘high’ level, theB bank 100 b is allocated as the first input/output port dedicated access area. The command signals CMD_B2, Fix_2 and Shared remain at logic ‘low’ level. - To allocate the
C bank 100 c as the second input/output port dedicated access area, an access path PA3 may be established between theC bank 100 c and the secondport control unit 300. That is, a C bank select signal CMD_C2 and the access path control command signal Fix_2 generated only for theC bank 100 c may be enabled. For example, as in theA bank 100 a, when the C bank select signal CMDL_C2 is applied at a logic ‘high’ level and when the signal Fix_2 generated only for theC bank 100 c is applied at a logic ‘high’ level, theC bank 100 c is allocated as the second input/output port dedicated access area. The command signals CMD_C1, Fix_1 and Shared remain at logic ‘low’ level. - To allocate the
D bank 100 d as the second input/output port dedicated access area, an access path PA4 may be established between theD bank 100 d and the secondport control unit 300. That is, when the D bank select signal CMD_D2 is applied at a logic ‘high’ level and when the signal Fix_2 generated only for theD bank 100 d is applied at a logic ‘high’ level, theD bank 100 d is allocated as the second input/output port dedicated access area. The command signals CMD_D1, Fix_1 and Shared remain at logic ‘low’ level. -
FIG. 10 illustrates an operation example in which theA bank 100 a is allocated as the first input/output port dedicated access area, and theB bank 100 b, theC bank 100 c, and theD bank 100 d are allocated as the second input/output port dedicated access area. - To allocate the
A bank 100 a as the first input/output port dedicated access area, an access path PA1 may be established between theA bank 100 a and the firstport control unit 200 as previously described with reference toFIG. 9 . - To allocate the
B bank 100 b as the second input/output port dedicated access area, an access path PA5 may be established between theB bank 100 b and the secondport control unit 300. That is, a B bank select signal CMD_B2 and the access path control command signal Fix_2 generated only for theB bank 100 b may be enabled. For example, when the B bank select signal CMD_B2 is applied at a logic ‘high’ level and when the signal Fix_2 for allocating theB bank 100 b as the second input/output port dedicated access area is applied at a logic ‘high’ level, theB bank 100 b is allocated as the second input/output port dedicated access area. The command signals CMD_B1, Fix_1 and Shared remain at logic ‘low’ level. - To allocate the
C bank 100 c and theD bank 100 d as the second input/output port dedicated access areas, access paths PA3 and PA4 may be established as previously described with reference toFIG. 9 . -
FIG. 11 shows an operation example in which theA bank 100 a, theB bank 100 b, theC bank 100 c, and theD bank 100 d are all allocated as the first input/output port dedicated access area. Thus, the multi-port semiconductor memory device can operate as a single port semiconductor memory device. - To allocate all of the
A bank 100 a, theB bank 100 b, theC bank 100 c, and theD bank 100 d as the first input/output port dedicated access area, access paths PA1, PA2, PA7, and PA8 may be established between therespective memory banks port control unit 200. An allocation operation example of setting theA bank 100 a and theB bank 100 b as the first input/output port dedicated areas has been described inFIG. 9 and, thus, a description thereof is omitted. - To allocate the
C bank 100 c as the first input/output port dedicated access area, an access path PA7 may be established between theC bank 100 c and the firstport control unit 200. When the C bank select signal CMD_C1 is applied at a logic ‘high’ level and when the signal Fix_1 for allocating theC bank 100 c as the first input/output port dedicated access area is applied at a logic ‘high’ level, theC bank 100 c is allocated as the first input/output port dedicated access area. The command signals CMD_C2, Fix_2 and Shared remain at logic ‘low’ level. - To allocate the
D bank 100 d as the first input/output port dedicated access area, an access path PA8 may be established between theD bank 100 d and the firstport control unit 200. When the D bank select signal CMD_D1 is applied at a logic ‘high’ level and when the signal Fix_1 for allocating theD bank 100 d as the first input/output port dedicated access area is applied at a logic ‘high’ level, theD bank 100 d is allocated as the first input/output port dedicated access area. The command signals CMD_C2, Fix_2 and Shared remain at logic ‘low’ level. -
FIG. 12 shows an operation example in which theA bank 100 a, theB bank 100 b, theC bank 100 c, and theD bank 100 d are all allocated as the second input/output port dedicated access area. As inFIG. 11 , this multi-port semiconductor memory device can operate as a single port semiconductor memory device. To allocate all of theA bank 100 a, theB bank 100 b, theC bank 100 c, and theD bank 100 d as the second input/output port dedicated access area, access paths PA3, PA4, PA5, and PA6 may be established between therespective memory banks port control unit 300. The allocation operation is similar to the operation described inFIG. 11 and need not be described in further detail. -
FIG. 13 illustrates an operation example in which theA bank 100 a is allocated as the first input/output port dedicated access area, theB bank 100 b as the shared access area, and theC bank 100 c and theD bank 100 d as the second input/output port dedicated access area. This case corresponds to a case in which there is the shared access area which can be accessed at both the first and second input/output ports. - An access path PA1 may be established in order to allocate the
A bank 100 a as the first input/output port dedicated access area. Further, access paths PA3 and PA4 may be established between therespective C bank 100 c and theD bank 100 d and the secondport control unit 300 in order to allocate theC bank 100 c and theD bank 100 d as the second input/output port dedicated access area. These allocation operations have been previously described inFIGS. 9 to 12 and need not be described in further detail. - To allocate the
B bank 100 b as the shared access area, the access path PA2 with the firstport control unit 200 and the access path PA5 with the secondport control unit 300 may be established. To this end, the signal Shared for allocating theB bank 100 b as the shared access area may first be applied at a logic ‘high’ level. In this state, an access operation may be performed through a desired one of the access path PA2 with the firstport control unit 200 and the access path PA5 with the secondport control unit 300. For example, the B bank select signal CMD_B1 may be applied at a logic ‘high’ level through the first port control unit in order to access theB bank 100 b through the first input/output port. The B bank select signal CMD_B2 may then be applied at a logic ‘high’ level through the second port control unit in order to access theB bank 100 b through the second input/output port. Thus, the access path may be determined depending on an input/output port used to apply the B bank select signal CMD_B1 or CMD_B2 at a logic ‘high’ level. Even when the signal Shared for allocating theB bank 100 b as the shared access area is applied at a logic ‘high’ level, the first select control signal and the second select control signal for controlling the access paths PA2 and PA5 do not become a logic ‘high’ level. This provides an advantage of preventing collision between the input/output ports in the shared access area. The order of applying the command signals Shared, CMD_B1 and CMD_B2 can be changed. -
FIG. 14 illustrates an operation example in which theA bank 100 a and theB bank 100 b are allocated as the shared access area, and theC bank 100 c and theD bank 100 d as the second input/output port dedicated access area. In this case, the shared access area that can be accessed at both the first and second input/output ports includes two memory banks. - To allocate the
C bank 100 c and theD bank 100 d as the second input/output port dedicated access area, access paths PA3 and PA4 may be established between theC bank 100 c and theD bank 100 d and the secondport control unit 300 as previously described inFIGS. 9 to 13 . Further, an operation of allocating theB bank 100 b as the shared access area has been described inFIG. 13 and, thus, a description thereof is omitted. - To allocate the
A bank 100 a as the shared access area, the access path PA1 with the firstport control unit 200 and the access path PA6 with the secondport control unit 300 may be established. To this end, the signal Shared for allocating theA bank 100 a as the shared access area may first be applied at a logic ‘high’ level. In this state, an access operation may be performed through a desired one of the access path PA1 with the firstport control unit 200 and the access path PA6 with the secondport control unit 300. For example, the A bank select signal CMD_A1 may be applied at a logic ‘high’ level through the firstport control unit 200 in order to access theA bank 100 a through the first input/output port. The A bank select signal CMD_A2 may be applied at a logic ‘high’ level through the second port control unit in order to access theA bank 100 a through the second input/output port. Thus, the access path may be determined depending on an input/output port used to apply the A bank select signal CMD_A1 or CMD_B2 at a logic ‘high’ level. This provides an advantage of preventing collision between the input/output ports in the shared access area. The order of applying the command signals Shared, CMD_A1 and CMD_A2 can be changed. -
FIG. 15 illustrates an operation example in which allmemory banks FIG. 15 , access paths PA1, PA2, PA5 and PA6 may be established to allocate theA bank 100 a and theB bank 100 b as the shared access area as previously described inFIGS. 13 and 14 . - To allocate the
C bank 100 c as the shared access area, the access path PA7 with the firstport control unit 200 and the access path PA3 with the secondport control unit 300 may be established. To this end, the signal Shared for allocating theC bank 100 c as the shared access area may first be applied at a logic ‘high’ level. In this state, an access operation may be performed through a desired one of the access path PA7 with the firstport control unit 200 and the access path PA3 with the secondport control unit 300. For example, the C bank select signal CMD_C1 is applied at a logic ‘high’ level through the firstport control unit 200 in order to access theC bank 100 c through the first input/output port. The C bank select signal CMD_C2 is applied at a logic ‘high’ level through the second port control unit in order to access theC bank 100 c through the second input/output port. In theC bank 100 c, access collision is prevented between the input/output ports. The order of applying the command signals Shared, CMD_C1 and CMD_C2 can be changed. - To allocate the
D bank 100 d as the shared access area, the access path PA8 with the firstport control unit 200 and the access path PA4 with the secondport control unit 300 may be established. To this end, the signal Shared for allocating theD bank 100 d as the shared access area is first applied at a logic ‘high’ level. In this state, an access operation may be performed through a desired one of the access path PA8 with the firstport control unit 200 and the access path PA4 with the secondport control unit 300. For example, the D bank select signal CMD_D1 is applied at a logic ‘high’ level through the firstport control unit 200 in order to access theD bank 100 d through the first input/output port. The D bank select signal CMD_D2 is applied at a logic ‘high’ level through the second port control unit in order to access theD bank 100 d through the second input/output port. In theD bank 100 d, access collision is prevented between the input/output ports, as well. The order of applying the command signals Shared, CMD_D1 and CMD_D2 can be changed. - The semiconductor memory device as described above according to an embodiment of the invention is also useful for testing. That is, the semiconductor memory device has an advantage when performing a test according to conditions by controlling the access paths in a given test environment.
- For example, when the number of test pins of test equipment needs to be reduced, all of the
memory banks FIG. 11 or the second input/output port dedicated access area as inFIG. 12 . Then, the test may be performed through the first input/output port or the second input/output port. Accordingly, the number of the test pins can be reduced. In this case, other memory devices may be tested using remaining test pins. - As another example, in order to reduce a test time, the
memory banks FIG. 9 . Then, testing may be performed through the first input/output port or the second input/output port. Accordingly, the test time can be reduced. - In addition, efficient testing can be achieved by controlling the access paths according to a test environment. Control of the access paths for the test operation may be performed through the operation as described in
FIGS. 2 to 15 . In this case, however, the external command signal may be an external command signal for test (e.g., MRS signal for test) or a combination of other input command signals. - According to the invention as described above, the access paths used to access the memory areas constituting the multi-port semiconductor memory device through the respective input/output ports may be variably controlled. Thus, the memory areas can be efficiently utilized by a user. In addition, the test according to a test environment is possible and, thus, efficient testing can be performed.
- Having described exemplary embodiments of the invention, it should be apparent that modifications and variations can be made by persons skilled in the art in light of the above teachings. Therefore, it is to be understood that changes may be made to embodiments of the invention disclosed that are nevertheless within the scope and the spirit of the claims.
Claims (7)
1. A semiconductor memory device comprising:
a plurality of input/output ports;
a memory array divided into a plurality of memory areas; and
a select control unit to establish variable access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports, wherein the select control unit establishes the variable access paths directly in response to command signals external to the memory device, wherein
the memory array is divided into at least four memory areas; and
the select control unit is structured to establish a first data path and a first address path between a first input/output port and a first of the at least four memory areas, to establish a second data path and a second address path between a second input/output port and a second of the at least four memory areas, to establish a third data path and a third address path between the first input/output port and a third of the at least four memory areas, and to establish a fourth data path and a fourth address path between the second input/output port and a fourth of the at least four memory areas, in response to the command signals external to the memory device,
wherein when the memory device is operating, the command signals external to the memory device are transmitted via:
at least four first signal terminals, the external command signals transmitted via at least one of the first signal terminals being structured to establish a data path and an address path between one of the four memory areas and the first input/output port; and
at least four second signal terminals, the external command signals transmitted via at least one of the second signal terminals being structured to disable a data path and an address path between one of the four memory areas and the second input/output port.
2. The device according to claim 1 , wherein the select control unit operates in a normal operation mode in response to external command signals for a normal operation and operates in a test mode in response to external command signals for a test operation.
3. A semiconductor memory device comprising:
first and second input/output ports;
a memory array divided into a plurality of memory areas; and
a select control unit to establish variable access paths between the memory areas and the first and second input/output ports such that each memory area is variably allocated as one of a first input/output port dedicated access area, a second input/output port dedicated access area, and a shared access area, wherein the select control unit variably allocates the memory areas directly in response to command signals external to the memory device, wherein the select control unit comprises:
a command multiplexer to generate select control signals in response to the external command signals, wherein the select control signals allocate each memory area as one of the first input/output port dedicated access area, the second input/output port dedicated access area, and the shared access area;
a data multiplexer to control data paths between the input/output ports and the memory areas in response to the select control signals; and
an address multiplexer to control address paths between the input/output ports and the memory areas in response to the select control signals;
wherein the select control unit variably allocates the memory areas;
wherein the select control unit operates in a normal operation mode in response to external command signals based on an MRS code signal for a normal operation and operates in a test mode in response to external command signals based on an MRS code signal for a test operation;
wherein when the memory device is operating, the external command signals are transmitted via:
at least four first signal terminals, the external command signals transmitted via at least one of the first signal terminals being structured to establish a data path and an address path between one of at least four memory areas and the first input/output port;
at least four second signal terminals, the external command signals transmitted via at least one of the second signal terminals being structured to disable a data path and an address path between one of the four memory areas and the second input/output port; and
at least four shared signal terminals, the external command signals transmitted via at least one of the shared signal terminals being structured to establish a data path and an address path between one of the four memory areas and both the first and second input/output ports.
4. In a semiconductor memory device comprising a plurality of input/output ports and a memory array divided into a plurality of memory areas, a method for variably accessing the memory areas, comprising:
applying external command signals to allocate the memory areas for access through at least one of the input/output ports;
establishing data and address paths between the memory areas and corresponding input/output ports according to the memory area allocation;
re-applying the external command signals to re-allocate the memory areas for access through different input/output ports; and
establishing new data and address paths between the memory areas and the corresponding different input/output ports according to the memory area re-allocation, wherein the external command signals are transmitted via:
at least four first signal terminals, the external command signals transmitted via at least one of the first signal terminals establishing a data path and an address path between one of at least four memory areas and the first input/output port;
at least four second signal terminals, the external command signals transmitted via at least one of the second signal terminals disabling a data path and an address path between one of the four memory areas and the second input/output port; and
at least four shared signal terminals, the external command signals transmitted via at least one of the shared signals establishing a data path and an address path between one of the four memory areas and both the first and second input/output ports.
5. The method according to claim 4 , wherein when the semiconductor memory device has first and second input/output ports, each memory area is variably allocated as one of a first input/output port dedicated access area, a second input/output port dedicated access area, and a shared access area.
6. The method according to claim 4 , wherein each memory area is variably allocated based on an MRS code signal.
7. The method according to claim 1 , wherein when the memory device is operating, the command signals external to the memory device are transmitted via at least four shared signal terminals, the external command signals transmitted via at least one of the shared signal terminals being structured to establish a data path and an address path between one of the four memory areas and both the first and second input/output ports.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/401,766 US20090175114A1 (en) | 2005-12-22 | 2009-03-11 | Multi-port semiconductor memory device having variable access paths and method therefor |
US12/785,832 US8120986B2 (en) | 2005-12-22 | 2010-05-24 | Multi-port semiconductor memory device having variable access paths and method therefor |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2005-127534 | 2005-12-22 | ||
KR1020050127534A KR100655081B1 (en) | 2005-12-22 | 2005-12-22 | Multi-port semiconductor memory device having variable access path and method therefore |
US11/466,389 US7505353B2 (en) | 2005-12-22 | 2006-08-22 | Multi-port semiconductor memory device having variable access paths and method |
US12/401,766 US20090175114A1 (en) | 2005-12-22 | 2009-03-11 | Multi-port semiconductor memory device having variable access paths and method therefor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/466,389 Continuation US7505353B2 (en) | 2005-12-22 | 2006-08-22 | Multi-port semiconductor memory device having variable access paths and method |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/785,832 Division US8120986B2 (en) | 2005-12-22 | 2010-05-24 | Multi-port semiconductor memory device having variable access paths and method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090175114A1 true US20090175114A1 (en) | 2009-07-09 |
Family
ID=37732471
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/466,389 Active 2026-09-27 US7505353B2 (en) | 2005-12-22 | 2006-08-22 | Multi-port semiconductor memory device having variable access paths and method |
US12/401,766 Abandoned US20090175114A1 (en) | 2005-12-22 | 2009-03-11 | Multi-port semiconductor memory device having variable access paths and method therefor |
US12/785,832 Active US8120986B2 (en) | 2005-12-22 | 2010-05-24 | Multi-port semiconductor memory device having variable access paths and method therefor |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/466,389 Active 2026-09-27 US7505353B2 (en) | 2005-12-22 | 2006-08-22 | Multi-port semiconductor memory device having variable access paths and method |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/785,832 Active US8120986B2 (en) | 2005-12-22 | 2010-05-24 | Multi-port semiconductor memory device having variable access paths and method therefor |
Country Status (5)
Country | Link |
---|---|
US (3) | US7505353B2 (en) |
JP (1) | JP2007172811A (en) |
KR (1) | KR100655081B1 (en) |
CN (1) | CN1988033B (en) |
DE (1) | DE102006062399A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110047311A1 (en) * | 2009-08-24 | 2011-02-24 | Micron Technology, Inc. | Multi-port memory and operation |
TWI587134B (en) * | 2016-05-12 | 2017-06-11 | 廣達電腦股份有限公司 | Management method and management system |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100668756B1 (en) * | 2005-10-12 | 2007-01-29 | 주식회사 하이닉스반도체 | Semiconductor device |
KR100655081B1 (en) * | 2005-12-22 | 2006-12-08 | 삼성전자주식회사 | Multi-port semiconductor memory device having variable access path and method therefore |
KR100735612B1 (en) * | 2005-12-22 | 2007-07-04 | 삼성전자주식회사 | Multi-path accessible semiconductor memory device |
CN101702947B (en) * | 2007-04-12 | 2017-02-15 | 拉姆伯斯公司 | memory system with point-to-point request interconnect, memory controller and method |
US7554858B2 (en) * | 2007-08-10 | 2009-06-30 | Micron Technology, Inc. | System and method for reducing pin-count of memory devices, and memory device testers for same |
JP5599969B2 (en) * | 2008-03-19 | 2014-10-01 | ピーエスフォー ルクスコ エスエイアールエル | Multi-port memory and computer system including the multi-port memory |
JP5449686B2 (en) * | 2008-03-21 | 2014-03-19 | ピーエスフォー ルクスコ エスエイアールエル | Multiport memory and system using the multiport memory |
US8036061B2 (en) * | 2009-02-13 | 2011-10-11 | Apple Inc. | Integrated circuit with multiported memory supercell and data path switching circuitry |
FR2946441A1 (en) * | 2009-06-08 | 2010-12-10 | Commissariat Energie Atomique | NETWORK FOR INTERCONNECTIONS WITH DYNAMIC SUB-NETWORKS. |
DE102010052486B4 (en) * | 2010-11-26 | 2015-08-27 | Bombardier Transportation Gmbh | Control arrangement for controlling the operation of a track-bound vehicle and method for producing the control arrangement |
JP2012208975A (en) * | 2011-03-29 | 2012-10-25 | Renesas Electronics Corp | Semiconductor device |
US8611175B2 (en) | 2011-12-07 | 2013-12-17 | Xilinx, Inc. | Contention-free memory arrangement |
US9514069B1 (en) | 2012-05-24 | 2016-12-06 | Schwegman, Lundberg & Woessner, P.A. | Enhanced computer processor and memory management architecture |
JP2014067241A (en) * | 2012-09-26 | 2014-04-17 | Fujitsu Semiconductor Ltd | Semiconductor memory device and electronic device |
US9921980B2 (en) | 2013-08-12 | 2018-03-20 | Micron Technology, Inc. | Apparatuses and methods for configuring I/Os of memory for hybrid memory modules |
US11073553B2 (en) * | 2017-12-29 | 2021-07-27 | Texas Instruments Incorporated | Dynamic generation of ATPG mode signals for testing multipath memory circuit |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4796232A (en) * | 1987-10-20 | 1989-01-03 | Contel Corporation | Dual port memory controller |
US4967398A (en) * | 1989-08-09 | 1990-10-30 | Ford Motor Company | Read/write random access memory with data prefetch |
US5239509A (en) * | 1991-01-23 | 1993-08-24 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5276842A (en) * | 1990-04-10 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Dual port memory |
US5335199A (en) * | 1991-03-19 | 1994-08-02 | Fujitsu Limited | Multiport memory |
US5502683A (en) * | 1993-04-20 | 1996-03-26 | International Business Machines Corporation | Dual ported memory with word line access control |
US5659711A (en) * | 1991-03-13 | 1997-08-19 | Mitsubishi Denki Kabushiki Kaisha | Multiport memory and method of arbitrating an access conflict therein |
US5768211A (en) * | 1996-07-31 | 1998-06-16 | Cypress Semiconductor Corporation | Multi-port arbitration for high performance width expansion |
US5815456A (en) * | 1996-06-19 | 1998-09-29 | Cirrus Logic, Inc. | Multibank -- multiport memories and systems and methods using the same |
US6310818B1 (en) * | 2000-11-06 | 2001-10-30 | Fujitsu Limited | Semiconductor memory device and method of changing output data of the same |
US20020078311A1 (en) * | 2000-12-20 | 2002-06-20 | Fujitsu Limited | Multi-port memory based on DRAM core |
US20050111571A1 (en) * | 2003-10-14 | 2005-05-26 | Toppoly Optoelectronics Corp. | Method of transmitting data |
US20050249026A1 (en) * | 2004-05-06 | 2005-11-10 | Beom-Ju Shin | Synchronous memory device |
US20070022245A1 (en) * | 2005-07-25 | 2007-01-25 | Samsung Electronics Co., Ltd. | Method of controlling refresh operation in multi-port dram and a memory system using the method |
US7505353B2 (en) * | 2005-12-22 | 2009-03-17 | Samsung Electronics Co., Ltd. | Multi-port semiconductor memory device having variable access paths and method |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02123594A (en) * | 1988-11-02 | 1990-05-11 | Toshiba Corp | 2-port ram |
JPH0363995A (en) * | 1989-08-02 | 1991-03-19 | Nec Corp | Dual port memory |
JP3080520B2 (en) * | 1993-09-21 | 2000-08-28 | 富士通株式会社 | Synchronous DRAM |
JPH07319755A (en) | 1994-05-25 | 1995-12-08 | Nippon Telegr & Teleph Corp <Ntt> | Multi-port memory |
JP3497904B2 (en) * | 1995-02-03 | 2004-02-16 | 株式会社ルネサステクノロジ | Semiconductor device |
JPH09115286A (en) * | 1995-10-17 | 1997-05-02 | Hitachi Ltd | Multi-port memory |
DE19740695C2 (en) * | 1997-09-16 | 2002-11-21 | Infineon Technologies Ag | Multi-level hierarchy data storage |
JP2001043674A (en) | 1999-07-30 | 2001-02-16 | Fujitsu Ltd | Semiconductor memory |
JP4339534B2 (en) * | 2001-09-05 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | A semiconductor device with a memory chip and logic chip that enables testing of the memory chip |
KR100493028B1 (en) * | 2002-10-21 | 2005-06-07 | 삼성전자주식회사 | Circuit and method of generating mode register set(MRS) code in semiconductor memory device |
JP2004192694A (en) | 2002-12-10 | 2004-07-08 | Renesas Technology Corp | Semiconductor storage device |
-
2005
- 2005-12-22 KR KR1020050127534A patent/KR100655081B1/en active IP Right Grant
-
2006
- 2006-08-22 US US11/466,389 patent/US7505353B2/en active Active
- 2006-11-10 JP JP2006305893A patent/JP2007172811A/en active Pending
- 2006-12-15 CN CN2006101669668A patent/CN1988033B/en active Active
- 2006-12-20 DE DE102006062399A patent/DE102006062399A1/en not_active Withdrawn
-
2009
- 2009-03-11 US US12/401,766 patent/US20090175114A1/en not_active Abandoned
-
2010
- 2010-05-24 US US12/785,832 patent/US8120986B2/en active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4796232A (en) * | 1987-10-20 | 1989-01-03 | Contel Corporation | Dual port memory controller |
US4967398A (en) * | 1989-08-09 | 1990-10-30 | Ford Motor Company | Read/write random access memory with data prefetch |
US5276842A (en) * | 1990-04-10 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Dual port memory |
US5239509A (en) * | 1991-01-23 | 1993-08-24 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5659711A (en) * | 1991-03-13 | 1997-08-19 | Mitsubishi Denki Kabushiki Kaisha | Multiport memory and method of arbitrating an access conflict therein |
US5335199A (en) * | 1991-03-19 | 1994-08-02 | Fujitsu Limited | Multiport memory |
US5502683A (en) * | 1993-04-20 | 1996-03-26 | International Business Machines Corporation | Dual ported memory with word line access control |
US5815456A (en) * | 1996-06-19 | 1998-09-29 | Cirrus Logic, Inc. | Multibank -- multiport memories and systems and methods using the same |
US5768211A (en) * | 1996-07-31 | 1998-06-16 | Cypress Semiconductor Corporation | Multi-port arbitration for high performance width expansion |
US6310818B1 (en) * | 2000-11-06 | 2001-10-30 | Fujitsu Limited | Semiconductor memory device and method of changing output data of the same |
US20020078311A1 (en) * | 2000-12-20 | 2002-06-20 | Fujitsu Limited | Multi-port memory based on DRAM core |
US20050111571A1 (en) * | 2003-10-14 | 2005-05-26 | Toppoly Optoelectronics Corp. | Method of transmitting data |
US20050249026A1 (en) * | 2004-05-06 | 2005-11-10 | Beom-Ju Shin | Synchronous memory device |
US20070022245A1 (en) * | 2005-07-25 | 2007-01-25 | Samsung Electronics Co., Ltd. | Method of controlling refresh operation in multi-port dram and a memory system using the method |
US7505353B2 (en) * | 2005-12-22 | 2009-03-17 | Samsung Electronics Co., Ltd. | Multi-port semiconductor memory device having variable access paths and method |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110047311A1 (en) * | 2009-08-24 | 2011-02-24 | Micron Technology, Inc. | Multi-port memory and operation |
WO2011028409A3 (en) * | 2009-08-24 | 2011-06-03 | Micron Technology, Inc. | Multi-port memory and operation |
EP2470999A2 (en) * | 2009-08-24 | 2012-07-04 | Micron Technology, Inc. | Multi-port memory and operation |
EP2470999A4 (en) * | 2009-08-24 | 2013-01-23 | Micron Technology Inc | Multi-port memory and operation |
JP2013506890A (en) * | 2009-08-24 | 2013-02-28 | マイクロン テクノロジー, インク. | Multiport memory and its operation |
US8769213B2 (en) | 2009-08-24 | 2014-07-01 | Micron Technology, Inc. | Multi-port memory and operation |
TWI456584B (en) * | 2009-08-24 | 2014-10-11 | Micron Technology Inc | Multi-port memory and operation |
US8930643B2 (en) | 2009-08-24 | 2015-01-06 | Micron Technology, Inc. | Multi-port memory and operation |
TWI587134B (en) * | 2016-05-12 | 2017-06-11 | 廣達電腦股份有限公司 | Management method and management system |
Also Published As
Publication number | Publication date |
---|---|
US7505353B2 (en) | 2009-03-17 |
US20070147162A1 (en) | 2007-06-28 |
CN1988033B (en) | 2012-05-30 |
KR100655081B1 (en) | 2006-12-08 |
US20100232249A1 (en) | 2010-09-16 |
US8120986B2 (en) | 2012-02-21 |
DE102006062399A1 (en) | 2007-06-28 |
JP2007172811A (en) | 2007-07-05 |
CN1988033A (en) | 2007-06-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7505353B2 (en) | Multi-port semiconductor memory device having variable access paths and method | |
US6166942A (en) | Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines | |
KR100609038B1 (en) | Multi-port memory device having serial i/o interface | |
US6381190B1 (en) | Semiconductor memory device in which use of cache can be selected | |
US7499364B2 (en) | Multi-port semiconductor memory device and signal input/output method therefor | |
KR100745369B1 (en) | Multi-path accessible semiconductor memory device having port states signaling function | |
US6243279B1 (en) | Semiconductor integrated circuit device | |
US6324104B1 (en) | Semiconductor integrated circuit device | |
US6154864A (en) | Read only memory embedded in a dynamic random access memory | |
US8024627B2 (en) | Semiconductor memory device, operating method thereof, and compression test method thereof | |
US20090059696A1 (en) | Multi-port memory device | |
US6339817B1 (en) | Semiconductor memory including main and sub memory portions having plural memory cell groups and a bidirectional data transfer circuit | |
US20090024803A1 (en) | Multipath accessible semiconductor memory device having shared register and method of operating thereof | |
US7289385B2 (en) | Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method | |
KR101430687B1 (en) | Multi processor system having direct access booting operation and direct access booting method therefore | |
US6418072B2 (en) | Semiconductor integrated circuit | |
US6728159B2 (en) | Flexible multibanking interface for embedded memory applications | |
US20090019237A1 (en) | Multipath accessible semiconductor memory device having continuous address map and method of providing the same | |
US8385145B2 (en) | Semiconductor memory apparatus | |
US20030107910A1 (en) | Integrated memory, and a method of operating an integrated memory | |
KR20010003827A (en) | Semiconductor device having data multiplexing and data masking function | |
KR20010027373A (en) | Semiconductor having static memory cell array area and dynamic memory cell array area in the same memory area |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |