US4896262A - Emulation device for converting magnetic disc memory mode signal from computer into semiconductor memory access mode signal for semiconductor memory - Google Patents
Emulation device for converting magnetic disc memory mode signal from computer into semiconductor memory access mode signal for semiconductor memory Download PDFInfo
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- US4896262A US4896262A US06/704,520 US70452085A US4896262A US 4896262 A US4896262 A US 4896262A US 70452085 A US70452085 A US 70452085A US 4896262 A US4896262 A US 4896262A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
Definitions
- the present invention relates generally to backing (bulk, auxiliary or secondary) storage devices and more particularly to semiconductor backing storage devices incorporated with a computer system or a multicomputer system.
- the backing storage device can store a great capacity of information data, but has shortcomings such that the access time is slow when compared with that of the main (internal or immediate access) memory arranged within the computer system.
- magnetic disc storage devices are usually incorporated with a computer system as backing storage memory. This is because the magnetic disc storage devices are of random access storage which can store a great capacity of information data.
- the random access means direct access in which any locations designated by addresses can be accessed (data are searched) within the same access time irrespective of the preceding access address.
- the magnetic disc storage device is made up of a plurality of discs rotating at a constant speed and a series of magnetic arms each provided with one or more reading/writing heads. Magnetic paint material is applied on both the surfaces of the disc. Information data are magnetically written in or read out of the disc surface by bringing the arm head near the surface of the rotating disc. The arm head can be moved to any required areas (recording tracks) of the disc surface in accordance with an instruction. Each disc surface has a great number of recording tracks, and the tracks are further divided into a great number of sections or sectors. In access to the above-mentioned magnetic disc device, it inevitably takes an access time of approximately 40 milliseconds.
- the access time of the magnetic disc is much longer than that of the main memory arranged within a computer system.
- FIFO first-in first-out buffers having a capacity of several words (bytes) are disposed in the interface between the computer and the backing storage.
- these buffers will not reduce the access time itself of the magnetic disc backing storage, but only attains the matching or synchronization between the two.
- multicomputer systems are well known.
- the system is made up of a plurality of computers, in which the main computer executes various complex operations or calculations while other computers execute input/output control or routine jobs under the supervisory control of the main computer.
- communication control systems shared memory systems and cross-call magnetic disc systems have conventionally been utilized.
- communication protocol software procedures
- the semiconductor backing storage device which can store a great capacity of information data and can transfer information data at high access speed in a magnetic disc access mode so as to be connectable to a multicomputer system already configured in magnetic disc access mode.
- the backing storage device comprises a semiconductor backing storage means for storing a great capacity of information data as an auxiliary storage means, and a backing storage control means connected between a computer and the semiconductor backing storage means, said control means transferring information data in magnetic disc access mode between the computer and said control means and in semiconductor memory access mode between said control means and said semiconductor backing storage means.
- said backing storage control means In transferring information data between the computer and said semiconductor backing storage means, said backing storage control means omits or prepares access control command signals peculiar to the magnetic disc access mode and converts address data peculiar to the magnetic disc access mode into those necessary for the semiconductor memory access mode.
- the backing storage device comprises one-word buffer means arranged, respectively, in computer bus driver/receiver means and storage bus driver/receiver means for temporarily storing information data in transferring data between the computer and said semiconductor backing storage means in order that the succeeding data address is converted and transferred to the buffer means while the current data are transferred from the buffer means.
- the backing storage device comprises one-word buffer means arranged in said semiconductor backing storage means for temporarily storing information data in transferring data between said backing storage control means and said semiconductor storage means in order that the succeeding data are ECC processed and transferred to the buffer means while the current data are transferred from the buffer means.
- the semiconductor backing storage means comprises semiconductor array control means including a first data logic port means for temporarily storing address data and information data supplied from a first backing storage controller means; a second data logic port means for temporarily storing address data and information data supplied from a second backing storage controller means; a control logic port means for storing and outputting control signals of READ, WRITE and WRITE CHECK supplied from said two backing storage control means separately; and cross-call control means for designating one of said two data logic port means in response to the control signals output from said control logic port means under priority or first-in first-out condition, designating specific addresses in semiconductor storage means for data output from said designated data logic port means, and interlocking the address data and information data stored in one of said two data logic ports in case both said two backing storage control means generate access signals to said shared backing storage means simultaneously.
- FIG. 1 is a schematic block diagram showing a backing storage controller according to the present invention, which is arranged between a CPU of a computer system and a semiconductor backing storage device;
- FIG. 2 is a control flowchart of the backing storage controller shown in FIG. 1, which represents the control steps of transferring information data in magnetic discs access mode between the computer and the storage controller but in semiconductor memory access mode between the storage controller and the semiconductor backing storage;
- FIG. 3 is a schematic block diagram showing the semiconductor backing storage according to the present invention, which is made up of an array controller and a plurality of semiconductor storage arrays;
- FIG. 4 is a schematic block diagram showing the semiconductor storage array according to the present invention, which is made up of a semiconductor storage element, a logic circuit, a controller, a generator and buffers;
- FIG. 5 is a schematic block diagram of a buffer memory circuit according to the present invention, which is arranged in a computer bus driver/receiver or a storage bus driver/receiver both incorporated within the backing storage controller shown in FIG. 1 or in the array controller shown in FIG. 3;
- FIG. 6(A) is a timing chart for assistance in explaining conventional data access operation between the computer and backing storage device
- FIG. 6(B) is a timing chart for assistance in explaining data access operation between the computer and buffer memory circuit according to the present invention.
- FIG. 7 is a schematic block diagram showing a shared backing storage device according to the present invention arranged between two computers in a multicomputer system;
- FIG. 8 is a schematic block diagram showing an array controller according to the present invention, which is disposed between two backing storage controllers shown in FIG. 7 and a plurality of semiconductor storage arrays, in which three logic ports and a cross-call controller are additionally provided for the array controller shown in FIG. 3; and
- FIG. 9 is a schematic block diagram showing a plurality of backing storage devices according to the present invention arranged in parallel between two computers in a multicomputer system.
- a computer system is roughly made up of a central processing unit (CPU) or a computer 1 including a CPU or computer bus 2 for transferring plural control signals and information data to and from the CPU 1 in a lump or group a backing storage controller 3, and a semiconductor backing storage unit 4, as shown in FIG. 1.
- the backing storage controller 3 serves as an interface between the CPU 1 and the semiconductor backing storage unit 4, so that a great capacity of information data are transferred between the two under the control of the backing storage controller 3.
- the transfer operation between the two is implemented in response to instructions or command signals generated by the storage controller 3.
- the transfer control command signals derived from the CPU 1 are in the same access mode as that of magnetic disc devices.
- the storage controller 3 In transferring data between the computer side and the backing storage side, the storage controller 3 omits some access control command signals peculiar to magnetic disc access mode and converts address data peculiar to magnetic disc access mode into those necessary for semiconductor memory access mode.
- the backing storage controller 3 emulates (imitates) a magnetic disc backing storage controller.
- the controller 3 is an intelligent controller having direct memory access functions and interrupt functions, which includes a microprocessor operated in accordance with control microprogram stored in a ROM arranged therewithin.
- intelligence means that the storage controller 3 can improve the performance by repeatedly implementing the transfer operations on the basis of calculations, decisions, checking functions, etc.
- the storage controller 3 can transfer for itself data between the internal memory in the CPU 1 and the backing storage 4 without depending upon control of the CPU 1 (i.e. direct memory access) or interrupt for itself data transfer operation in case errors are checked out (interrupt function).
- a host interface (magnetic disc controller or CPU) is disposed between the computer system and the magnetic disc backing storage devices.
- the above host-interface can access to magnetic disc devices by designating a cylinder address, track address, head address and a sector address.
- the cylinder address decides a phantom cylinder formed by a plurality of equidiameter tracks of separate discs.
- the head address decides an arm head accessible to a disc. Therefore, it is also possible to consider that the head address and the track address designate one magnetic disc and the cylinder address designates one track on the designated discs.
- the number of sector pulses are counted by the magnetic head. The instant the number of sector pulses matches the sector address, a header (a set of data placed on top of a collection of data, which includes an identifier) is read out and then designated data are transferred.
- access control command signals are SEEK, READ, WRITE, READ HEADER, WRITE CHECK and further SELECT DRIVE, PACK ACKNOWLEDGE, DRIVE CLEAR, UNLOAD, START SPINDLE, RECALIBRATE, OFF-SET, WRITE HEADER, etc.
- the access control command signals other than SEEK, READ, WRITE, READ HEADER, and WRITE CHECK are omitted.
- the address data peculiar to magnetic disc mode are CYLINDER, TRACK, HEAD, and SECTOR; the address data peculiar to semiconductor access mode are ROW ADDRESS and COLUMN ADDRESS.
- the controller 3 is made up of a computer bus driver/receiver 5, an internal bus 6, a storage bus driver/receiver 7, an error correction code controller 8, a microprocessor 9, a microprogram sequencer 10, a read-only memory 11, registors 12, a condition code multiplexer 13, and a random-access memory 14.
- the computer bus driver/receiver 5 is disposed between the computer bus 2 and the internal bus 6 of the controller 3. This driver/receiver 5 receives from the CPU 1 data access control command signals, address data prepared in magnetic disk access mode, and information data to be written in the backing storage unit 4, and transmits to the CPU 1 control signals of DMA (direct memory access) and INTERRUPT (interrupt), address data prepared in magnetic disc access mode and information data to be read from the backing storage unit 4.
- DMA direct memory access
- INTERRUPT interrupt
- the storage bus driver/receiver 7 is disposed between the internal data bus 6 and the semiconductor backing storage unit 4. This driver/receiver 7 receives information data read from said backing storage unit 4, and transmits control command signals of READ, WRITE, WRITE CHECK, address data necessary for semiconductor memory access, and information data to be written in the backing storage unit 4.
- the error correction code controller 8 is connected to the internal data bus 6. This controller 8 adds an automatic error correction code (ECC) to data for each sector (which is sent from the CPU 1) and prepares data to be written into the backing storage unit 4. Further, this controller 8 checks the automatic error correction code (ECC) added to the data for each sector (which is read out of the unit 4) and further supplies information necessary for correcting erroneous data in case of the presence of an error.
- ECC automatic error correction code
- the above error correction code can not only detect an occurrence of error but also correct the detected error data to provide correct data in the case where the detected error satisfies a predetermined condition.
- a predetermined condition As an example, it is possible to give hamming code.
- each character is so expressed in codes as to have a minimum hamming distance (signal distance) from any other characters.
- an automatic error correction code controller is provided in an interface within the backing storage unit 4, in which each data word is automatically corrected.
- the computer bus driver/receiver 5 outputs access control command signals (READ, WRITE) to the condition code multiplexer 13, to which various control command signals generated within the backing storage controller 3 are inputted.
- This multiplexer 13 poll-scans the access control command signals from the computer bus driver/receiver 5 together with other control command signals in order to check sequentially whether the CPU 1 outputs an access request command signal. When checking the presence of access request command signal, the multiplexer 13 outputs an access command signal.
- the microprogram sequencer 10 In response to this access command signal and clock pulse signals CLK, the microprogram sequencer 10 generates microprogram address designation signals in sequence. In response to these microprogram address designation signals, the microprogram is derived from the read-only memory 11.
- the conditions here means various states to be executed by the microprocessor 9.
- the poll means a method of avoiding contention.
- the microprocessor 9 executes data transfer operations (WRITE, READ) to or from the backing storage unit 4 in response to information transfer request command signals in accordance with microprogram stored in the microprogram memory (ROM) 11.
- the above microprogram is formed by plural machine language sets and executes desired microinstructions in response to clock pulse signals. That is to say, the microprogram is read out from the microprogram memory (ROM) 11 on the basis of microprogram address designation signals generated by the microprogram sequencer 10, transferred to the register 12, and then given to the microprocessor 9 from the register 12 as microinstructions in response to clock pulse signals CLK applied to the register 12.
- the register 12 which receives the microprogram from the ROM 11 gives back necessary information such as instructions and the succeeding sequencer address to the microprogram sequencer 10.
- the sequencer 10 receives information from the condition code multiplexer 13.
- the parameter memory (RAM) 14 stores temporarily various signals indicative of address, data, control, etc. given from the internal data bus 6 and outputs these necessary signals to the microprocessor 9 at appropriate timing.
- the program control executed in the backing storage controller 3 will be described in detail with reference to a flowchart shown in FIG. 2.
- the control program first reads the characteristics of the backing storage unit 4 (e.g. the number of semiconductor elements, the configuration mode thereof, the capacity thereof, the access mode thereof, etc.) (in step S 1 ). That is to say, in this step, the number of semiconductor storage units and the capacity (megabyte memory modules) of semiconductor unit are checked and read in dependence upon the positions of switches attached to the storage unit 4. Control initializes the register 12 and other internally incorporated registers (in step S 2 ).
- Control allows the condition code multiplexer 13 to check whether the CPU bus driver/receiver 5 receives an access command signal from the CPU 1 in accordance with poll scanning method (in step S 3 ). Once control recognizes the presence of an access command signal from the CPU 1, control first analyzes the contents of hardware register incorporated within the storage controller 3, in which access command signals not related to data transfer between the CPU 1 and the backing storage 4 are temporarily stored (in step S 4 ).
- step S 5 if the contents of the hardware register is a read request not related to data transfer between CPU 1 and unit 4, data corresponding to the read request are sent from the RAM 14 to the CPU 1 through the computer bus driver/receiver 5, and thereafter control returns to step S 3 above.
- the above steps from S 3 to S 5 are executed repeatedly.
- step S 5 if the contents of the hardware register is a write request not related to data transfer between CPU 1 and unit 4, data corresponding to the write request are sent from the CPU 1 to the RAM 14 through the computer bus driver/receiver 5, and thereafter control returns to step S 3 above.
- the above steps from S 3 to S 5 are executed repeatedly.
- step S 5 if the contents of the hardware register is a read or write request related to data transfer between CPU 1 and unit 4, these requests are written in command registers (in step S 6 ).
- Control analyzes the access functions stored in the command register (in step S 7 ). If the analyzed access functions of the control command signals are peculiar to magnetic discs, that is, not required for the semiconductor disc element, these non-required command signals are passed without any processings (in step S 8 ) and control ends data transfer functions (in step S 9 ).
- Command signals to be passed in this step S 8 are SELECT DRIVE (to drive a selected disc), PACK ACKNOWLEDGE (to select one of several discs), DRIVE CLEAR (to return to its initial condition), UNLOAD (to return a head to an initial unaccessible position), START SPINDLE (to start a spindle motor), RECALIBRATE (to calibrate the whole disc condition), OFFSET (to offset a head position from a reference value), WRITE HEADER (a header data peculiar to discs), etc.
- step S 9 if interrupt processing is required due to the presence of an error, for instance, control informs the CPU 1 of the end of data transfer operation by interrupting the operation (in step S 10 ), returning to step S 3 . If no interrupt processing is required, control directly returns to step S 3 .
- step S 7 if the analyzed command functions are SEEK (to select and move a head), READ (to read data), WRITE (to write data), READ HEADER (to read header data), WRITE CHECK (to check written data) (in step S 11 ), the addresses of these command signals are checked. If the checked address is not correct, control outputs SEEK to return to the transfer function end processing of step 9 (in step 12). If the checked address is correct and control reads READ HEADER, control prepares header data in magnetic disc access mode on the basis of calculations executed by the microprocessor 9 in accordance with microprogram. The prepared header data are sent to the CPU 1 through the CPU bus 2 in dependence upon direct memory access (in step 13). Thereafter, control returns to transfer function end processing of step 9.
- SEEK to select and move a head
- READ to read data
- WRITE to write data
- READ HEADER to read header data
- WRITE CHECK to check written data
- step S 12 if the instructions (READ, WRITE, WRITE CHECK) are correct, control converts a magnetic disc address accessible to the CPU 1 into a semiconductor memory address accessible to the semiconductor storage unit 4 (in step S 14 ).
- This conversion step is also executed in accordance with a microprogram stored in the ROM 11 and on the basis of the backing storage characteristics already detected in step S 1 above.
- the magnetic disc address data include sector recognizing data such as preamble, postamble, and ID (identification label); however, the semiconductor storage unit 4 does not require such data.
- the address data necessary in magnetic disc access mode are CYLINDER, TRACK, HEAD, and SECTOR; the address data necessary in semiconductor access mode are ROW ADDRESS and COLUMN ADDRESS.
- step S 16 When data are written in each sector, there exists a case where all the addresses of one sector are not filled up by the data and some addresses are left unwritten. Therefore, after the data for each sector have been transferred, the remaining empty addresses are filled up by an appropriate digit (e.g. "0") (in step S 17 ).
- step S 18 Thereafter, in the case where data are written in the semiconductor unit 4, an error correction code is added to the transferred data by means of the error code correction controller 8; in the case where data are read out of the semiconductor unit 4, the added error correction code is extracted (in step S 18 ). Further, control checks whether there exists an error on the basis of the error correction code (in step 19). If no error is found in step 19, control checks whether a word counter reaches zero or not (in step S 20 ). This word counter is set in the microprocessor 9 in response to a command signal supplied from the CPU 1. If this word counter reaches zero, since the necessary number of words have been transferred, control returns to data transfer function end (in step S 9 ).
- step S 19 if an error is detected on the basis of error correction code, the detected error is automatically corrected (in step S 21 ). Thereafter, control ends data transfer function (in step S 9 ). In this case, if interruption is necessary due to error, for instance, control interrupts the succeeding processing (in step S 10 ) and returns to step S 3 for repeating the same transfer operations. If interruption is unnecessary, control directly returns to step S 3 for continuously repeating the same transfer operations.
- the CPU 1 requests data transfer to the backing storage unit 4 in magnetic disc access mode
- the storage controller 3 omits control data peculiar to magnetic disc access mode and converts address data peculiar to magnetic disc access mode into those peculiar to semiconductor element access mode, it is possible to directly transfer information data between the CPU 1 and the semiconductor unit 4.
- the backing storage unit 4 is roughly made up of a storage array controller 15, a bus 16, and plural semiconductor memory arrays 17 1 , . . . 17 n . Further, the storage array controller 15 is made up of an address controller 18, an ECC (error correction code) controller 19, a control signal generator 20, and a sequence controller 21.
- ECC error correction code
- the address designation data are applied through the backing storage driver/receiver 7 from the storage controller 3 to the address controller 18 incorporated within the semiconductor array controller 15.
- data to be read or written are transferred through the same storage driver/receiver 7 between the storage controller 3 and the word error correction code (ECC) controller 19 incorporated within the semiconductor array controller 15.
- ECC word error correction code
- the address controller 18 selects an area allocated to one of the storage arrays 17 1 . . . 17 n on the basis of the address data supplied from the storage controller 3 and outputs address selection signals together with the address designation signals.
- the ECC controller 19 adds a word error correction code (WORD ECC) to data to be written and extracts a word error correction code included in read data. In case an error is found, the controller 19 automatically corrects data to be transferred and transfers the corrected data between the storage controller 3 and the storage arrays 17 1 . . . 17 n .
- WORD ECC word error correction code
- the control signal generator 20 generates various control signals necessary for writing and reading data into or out of the storage arrays 17 1 . . . 17 n .
- These control signals are, for instance, row address strobe signal (RAS), column address strobe signal (CAS), write enable signal (WE), read-enable signal (RE), and drive-enable signal (DREN) in the case where a dynamic RAM is used for the semiconductor storage unit 4.
- strobe signals is a kind of clock signals to activate rows or columns sequentially.
- the sequence controller 21 controls input/output operation sequence of the controllers 18 and 19 and the control signal generator 20.
- the storage array controller 15 is connected to the storage arrays 17 1 . . . 17 n via the bus 16 in order to designate addresses of the arrays and to control reading and writing of data between the storage controller 3 and the storage arrays 17.
- the backing storage unit 4 is volatile memory such as dynamic semiconductor memory, since the stored data are destroyed when the power supply is off, it is necessary to provide a battery backup apparatus for the backing storage unit 4.
- a semiconductor storage 17 n of dynamic RAM type will be described in detail with reference to FIG. 4.
- the storage 17 includes an address selection logic circuit 22, a write buffer 26, an address matrix selection controller 23, a write-enable signal generator 24 and a read buffer 25.
- the address selection logic circuit 22 is connected between the address controller 18 and the semiconductor storage element 27 and generates address data signals to the storage element 27 in response to address data signal outputted from the address controller 18 and bus reflesh cycle signals.
- the address matrix selection controller 23 is connected between the control signal generator 24 and the storage element 27 and to the address election logic circuit 22 and generates row address selection strobe signals (RAS) and column address selection strobe signals (CAS) in sequence to the storage element in response to these strobe signals (RAS, CAS) and in synchronization with the address data signal.
- RAS row address selection strobe signals
- CAS column address selection strobe signals
- the write enable signal generator 24 is connected between the control signal generator 20 and the storage elements 27 and to the address selection logic circuit 22 and generates write control signal (WR) to the storage element 27 in response to the write enable signal (WE) and in synchronization with the address data signal.
- the write buffer 26 is connected between the error correction code controller 19 and the storage element 27 and writes information data in the storage element 27 in response to the write control signal (WR) applied from the write enable signal generator 24 to the element 27.
- WR write control signal
- the read buffer 25 is connected between the control signal generator 20 and the error correction code controller 19, and the storage element 27 and to the address selection logic circuit 22 and reads information data from the storage element 27 in response to the data read signal (RE) and the address data signal.
- FIFO first-in first-out
- the second feature of the present invention is to provide one-word buffers in the interface (storage controller 3 shown in FIG. 1) disposed between the computer system 1 and the backing storage unit 4. Additionally, the one-word buffers are provided for the ECC controller 19 of the array controller 15 (shown in FIG. 3) incorporated within the backing storage unit 4 in order to improve data transfer speed between the storage controller 3 and the storage array 17.
- the computer bus driver/receiver 5 and the storage bus driver/receiver 7 are each provided with one-word buffers for temporarily storing information data in transferring data between the CPU 1 and the backing storage unit 4.
- FIG. 5 shows an exemplary configuration of only the one-bit buffer. Therefore, each one-word buffer is made up of a plurality of one-bit buffers.
- the one-bit buffer is made up of a first data-latch type flip-flop FF 1 , a second data-latch type flip-flop FF 2 , an AND gate, several inverters 1, 2, 3, 4, 5 and 6, and two buffer amplifiers 1 and 2, for instance.
- the flip-flops FF 1 and FF 2 have a data input terminal D, a data output terminal Q and a clock pulse signal terminal C, respectively.
- Data transferred through a first bus line L 1 is supplied to the data input terminal D of the first flip-flop FF 1 via the buffer amplifier 1; an internal buffer command signal INT BUFF and another control signal CONT are applied to the clock pulse terminal C of the first flip-flop FF 1 via the AND gate and the inverter INV 1; an output signal (e.g. "1") of the first flip-flop FF 1 is applied to a second bus line L 2 via the inverter 3; a write-enable signal WE is applied to the inverter 3 via the inverter 2 to activate the inverter 3.
- Data transferred through the second bus line L 2 is supplied to the data input terminal D of the second flip-flop FF 2 via the inverter 4; a read-enable signal RE is applied to the clock pulse terminal C of the second flip-flop FF 2 via the inverter 5 and to the buffer amplifier 2 via the inverter 6; an output signal (e.g. "1") of the second flip-flop FF 2 is supplied to the first bus line L 1 via the buffer amplifier 2 activated by the inverter 6.
- the data on the first bus line L 1 is latched by the first flip-flop FF 1 via the data terminal D thereof when an internal buffer command signal INT BUFF and the control signal CONT are applied to the clock terminal C thereof simultaneously, and then outputted to the second bus line L 2 from the output terminal Q thereof when a write-enable signal WE is applied to the inverter 2 to activate the inverter 3.
- the data on the second bus line L 2 is latched by the second flip flop FF 2 via the data terminal D thereof when a read-enable signal RE is applied to the clock terminal C thereof, and then outputted to the first bus line L 1 from the output terminal Q thereof when the read-enable signal RE is reversed in polarity to activate the buffer amplifier 2.
- data are transferred between the computer system 1 and the backing storage unit 4 via the storage controller 3.
- the storage controller 3 converts address data prepared in magnetic disc access mode into those prepared in semiconductor element access mode in accordance with microprogram (in step S 14 shown in FIG. 2) and sends the converted address data to the semiconductor backing storage unit 4 as a leading address of data to be read out.
- the storage unit 4 stores this leading address.
- data stored in the semiconductor storage element are transferred into the buffer, thereafter incrementing the address automatically. Repeating the above-mentioned steps sequentially, data are transferred.
- FIG. 6A shows the case where the buffer memory are not provided.
- one-word data shown by (b) in FIG. 6(A) are read from the backing storage side 4 to the computer side 1 in response to a first read command as shown by (a) in FIG. 6(A).
- the time t 1 indicates an access time required for the semiconductor array;
- the time t 2 indicates an actual transfer time required for transferring data from the backing storage unit 4 to the computer 1 in accordance with direct access memory method.
- the total time T 1 is an addition of t 1 and t 2 .
- FIG. 6(B) shows the case where one-word buffers memory are provided.
- one-word data shown by (b) in FIG. 6(B) are first read from the backing storage side 4 to the one-word buffer in response to a first read command signal as shown by (a) in FIG. 6(B).
- the one-word data N is transferred from the buffer to the computer side 1 in accordance with direct access memory method
- address data of the succeeding one-word data N+1 shown by (b) in FIG. 6(B) are converted in response to the second read command signal and stored in the buffer.
- the transfer time T 2 is either longer one of the time required for data access (data conversion) or the time required for actual data transfer (from buffer to the computer), being capable of reducing the transfer time to approximately half of the conventional total transfer time T 1 .
- this buffer serves to reduce transfer time in reading information data from the backing storage unit 4 to the computer 1.
- this buffer serves to reduce error correction code processing time. That is to say, while the controller 15 adds or extracts an error correction code to or from the transfer data, the preceding data stored in the buffer are sent from the ECC controller 19 to the storage controller 3 or to the storage arrays 17.
- one-word data buffer memory units are provided respectively for both the storage controller 3 (driver/receivers 7) and the ECC controller 19, it is possible to convert address data of the present data or execute error correction code processing for the present data while transferring the preceding data stored in the buffer. Therefore, it is possible to transfer data at high speed in synchronization with the transfer operation of direct memory access between the backing storage unit 4 and the computer 1.
- FIFO first-in first-out
- the third feature of the present invention is to provide a shared memory which can read and write a great capacity of data at a high access speed and in cross-call method.
- FIG. 7 shows an embodiment in which a semiconductor backing storage unit 4a according to the present invention is used as a shared memory for a multicomputer system.
- a plurality of computers 1A and 1B having an internal memory unit, respectively, therewithin are connected to a shared semiconductor backing storage memory 4a through a storage controller 3A or 3B and a CPU bus 2A or 2B.
- the computer 1A or 1B requests information data transfer to the shared backing storage memory 4a in the same access mode as in a shared magnetic disc device. That is, the storage controller 3A or 3B omits some processings required for a magnetic disc and converts data address peculiar to magnetic disc into those required for semiconductor memory in order to allow information data outputted from the computer in magnetic disc access mode to be readable or writeable to or from the semiconductor memory unit of the shared backing storage 4a. Further, the shared backing storage 4a allows the semiconductor memory unit to be accessible in cross-call function.
- the configuration and operation of the storage controller 3A or 3B are quite the same as those of the storage controller 3 shown in FIG. 1 and described with reference to the flowchart shown in FIG. 2, therefore the description thereof being omitted herein.
- the storage unit 4a is roughly made up of a storage array controller 15a, a bus 16, and plural semiconductor memory arrays 17 1 . . . 17 n . Further, the storage array controller 15a is made up of an address controller 18, an ECC (error correction code) controller 19, a control signal generator 20, a sequence controller 21, and cross-call function section 22 having two data logic ports 22A and 22B provided with memory function, a control logic port 22C provided with memory function and a cross-call controller 22D.
- ECC error correction code
- the storage controller 3A is connected to the data logic port 22A to transfer addresses and data associated with the computer 1A between the storage controller 3A and the shared backing storage 4a, and further connected to the control logic port 22C to apply control command signals (READ, WRITE, WRITE CHECK) to the port 22C.
- the storage controller 3B is connected to the data logic port 22B to transfer addresses and data associated with the computer 1B and further connected to the common control logic port 22C to apply control command signals (READ, WRITE, WRITE CHECK) to the port 22C.
- the cross-call controller 22D designates any one of the storage controllers 3A and 3B in response to the control signals applied to the control logic port 22C. If the storage controller 3A is designated, the cross-call controller 22D defines specific addresses to the data logic port 22A. If the storage controller 3B is designated, the cross-call controller 22D defines other specific addresses to the data logic port 22B. In case both the storage controllers 3A and 3B apply the control signals simultaneously to the control logic port 22C to request the use of the shared backing storage, the cross-call controller 22D allocates any one of the data logic ports 22A and 22B under priority or first-in first-out on the basis of interlock function.
- cross-call controller 22D activates the control signal generator 20 on the basis of interlock function or cross-call function to output control command signals (RAS, CAS, WE, DREN).
- the address data derived from the data logic ports 22A and 22B are given to the address controller 18.
- the information data derived from the data logic ports 22A and 22B are given to the error correction code controller 19.
- the address controller 18 selects areas allocated to one of the storage arrays 17 1 . . . 17 n on the basis of the address data supplied from the data logic ports 22A or 22B and outputs address selection signals together with the address designation signals.
- the ECC controller 19 adds a word error correction code (WORD ECC) to data to be written and extracts a word error correction code from read data. In case an error is found, the ECC controller 19 automatically corrects the transferred data to correct ones and transfers the corrected data between the storage controller 3A or 3B and the storage arrays 17 1 . . . 17 n .
- the control signal generator 20 generates various control signals necessary for writing and reading data into or out of the storage arrays 17 1 . . . 17 n .
- control signals are, for instance, row address strobe signal (RAS), column address strobe signal (CAS), write-enable signal (WE), read-enable signal (RE), and drive-enable signal (DREN) in the case where a dynamic RAM is used for the semiconductor storage unit 4.
- RAS row address strobe signal
- CAS column address strobe signal
- WE write-enable signal
- RE read-enable signal
- DREN drive-enable signal
- the sequence controller 21 controls input/output operation sequence of the controllers 18 and 19 and the control signal generator 20.
- the storage array controller 15a is connected to the storage arrays 17 1 . . . 17 n via the bus 16 in order to designate addresses of the arrays and to control data reading and writing on the basis of cross-call function.
- the backing storage device according to the present invention has been described of the embodiment in which a single backing storage device is incorporated with a single or plural computers. However, it is also possible to provide a plurality of semiconductor backing storage devices arranged in parallel with each other for a computer system or a multi-computer system.
- FIG. 9 shows an embodiment in which plural backing storage devices 4 1 . . . 4 n are incorporated with a pair of computers 3A and 3B.
- each computer 3A or 3B generates a backing storage device selection signal; this signal is applied to the backing storage devices 4 1 . . . 4 n through the computer buses; the cross-call controller 22D of the array controller 15a in each shared backing storage 4a (shown in FIG. 8) selects itself in response to this device selection signal.
- the advantages are: (1) it is possible to markedly reduce access time to approximately several hundred microseconds as compared with the conventional magnetic disc access time (several tens milliseconds); (2) computer systems can access the semiconductor backing storage devices in the same access mode as in magnetic disc; that is, it is possible to directly connect the semiconductor backing storage units according to the present invention to computer systems so configured as to access magnetic disc backing storage devices.
- the semiconductor backing storage device does not necessitate complicated protocol as in communication control systems, it is also possible to eliminate transfer delay time caused by software overhead. Further, since highly-integrated semiconductor memory elements have recently been developed, it is possible to realize a small-scale highly-reliable, great-capacity backing storage device. In addition, in the access method according to the present invention, data transfer between computers and backing storage device is implemented for only the actual data excluding bit-synchronizing data, it is also possible to enhance storage efficiency without storing extra data.
- the backing storage device since one-word buffers are provided for the storage controller and the backing storage device, respectively, it is possible to further improve data transfer speed.
- the backing storage memory since cross-call functions are provided for the array controller in the backing storage device, it is possible to directly connect the semiconductor storage devices as a shared backing storage to a multicomputer system so configured as to access magnetic disc backing storage.
Abstract
Description
Claims (12)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
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JP59033801A JPS60178564A (en) | 1984-02-24 | 1984-02-24 | Auxiliary storage device |
JP3379884A JPS60178563A (en) | 1984-02-24 | 1984-02-24 | Shared memory device |
JP3380284A JPS60178565A (en) | 1984-02-24 | 1984-02-24 | Auxiliary storage device |
JP59-33798 | 1984-02-24 | ||
JP59-33801 | 1984-02-24 | ||
JP59-33802 | 1984-02-24 |
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US06/704,520 Expired - Fee Related US4896262A (en) | 1984-02-24 | 1985-02-22 | Emulation device for converting magnetic disc memory mode signal from computer into semiconductor memory access mode signal for semiconductor memory |
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