US5596738A - Peripheral device control system using changeable firmware in a single flash memory - Google Patents
Peripheral device control system using changeable firmware in a single flash memory Download PDFInfo
- Publication number
- US5596738A US5596738A US08/421,462 US42146295A US5596738A US 5596738 A US5596738 A US 5596738A US 42146295 A US42146295 A US 42146295A US 5596738 A US5596738 A US 5596738A
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- flash memory
- memory chip
- changeable
- firmware
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/24—Loading of the microprogram
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
Definitions
- This invention relates in general to peripheral device control systems, and relates more particularly to such systems having improved capabilities for modifying the firmware or microcode therein.
- the memory chip may be buried inside the PCB, so that the PCB itself has to be removed before the memory chip can be accessed and changed, adding more cost to the firmware change process.
- One approach to reduce the cost of firmware changes is to employ a single microcontroller, but add a small set of "BOOT” firmware which is mask fabricated into the microcontroller, and substitute a random access memory (RAM) chip in place of the EPROM.
- the masked BOOT code from the microcontroller is used to "spin up" the disk drive device and position the read/write heads over a special track on the disk that contains the remaining firmware which is then downloaded from the disk to the RAM.
- the BOOT firmware then turns control over to the RAM-based code.
- the use of flash memory in this environment did present two significant problems. The first was the cost of flash memory technology itself, and the second was the need to be able to reprogram the flash memory without any masked BOOT code.
- the cost issue involves consideration of the cost savings which can be obtained with the use of flash memory if firmware changes are needed.
- One approach would be to utilize two flash memory chips, one containing the BOOT code and the other containing the changeable firmware. However, this is not totally attractive because of the added space requirement for the second chip on an already crowded PCB.
- the present invention solves the second problem of changing firmware with only a single microcontroller and a single flash memory chip, without the use of any masked BOOT code.
- desired changes in system firmware in a peripheral device control system are accomplished without the need for any masked BOOT code through a novel interconnection of a single flash memory chip and a digital signal processor having an amount of RAM therein sufficient to store firmware BOOT code for controlling the updating of the changeable firmware in the flash memory.
- this BOOT firmware is preprogrammed into the flash memory chip at specified locations.
- this preprogrammed BOOT code is read out of the flash memory into a RAM area of the digital signal processor.
- This BOOT code in the RAM can then be executed to control the writing of the modified functional firmware into the flash memory.
- FIG. 1 is a block diagram of a peripheral device control system embodying the present invention
- FIG. 2 is a representation of a typical distribution of the preprogrammed firmware and the changeable firmware in a flash memory chip in accordance with this invention.
- FIGS. 3-10 are flow charts illustrating various phases of the operation of the invention.
- FIG. 1 shows a block diagram of elements for one implementation of the present invention in connection with a disk drive system. Although the invention will be described in connection with a disk drive system, it will be understood that the invention is useful in control systems for other peripheral devices such as printers, tape drives and modems.
- FIG. 1 shows a microprocessor 8 such as a Zilog type Z86C94.
- This unit contains a number of elements including a digital signal processor (DSP) 11 having associated therewith a RAM memory area 22.
- Microprocessor 8 also includes a central processing unit (CPU) 9 having associated therewith a RAM memory area 25.
- memory 22 may have a capacity of 160 bytes and memory 25 has a capacity of 256 bytes.
- Information is transmitted to and from microprocessor 8 on a serial port by means of a transmit data (TXD) line and a receive data (RXD) line forming part of the well known standard RS232 interface.
- Microprocessor 8 operates to control one or more peripheral devices (not shown) such as a disk drive system in the present example.
- the system of FIG. 1 also includes a flash memory 21 which interacts with microprocessor 8 as described above to store firmware code for operation of the disk drive system and provide for updating of that firmware as required by the user.
- a flash memory is a type of non-volatile RAM.
- Flash memory 21 may be an ATMEL type 29C256 flash memory device, a 5 volt, page programmable, 32k by 8 bit device.
- each page in flash memory 21 has 64 bytes, which results in 512 pages/device, and has a page programming time of 10 msec.
- the microprocessor runs at 20Mhz and the access time of flash memory 21 is 150 nSec. The timing for reading of the flash memory can be obtained without any wait state, but writing to the flash memory requires the microprocessor switch to a slower timing mode.
- Microprocessor 8 communicates with flash memory 21 over an address bus 10 and a data bus 12.
- the flash memory locks out all access to any other part of the memory. This can cause a problem with most microprocessors in that they must continue to execute code out of the same memory chip.
- the solution for this problem in the present invention is to allow the microcontroller to execute code from its own internal RAM 22.
- the microprocessor loads internal data RAM 22 with the flash memory BOOT code by moving preprogrammed control code from the flash memory preprogrammed BOOT area to RAM 22 on data bus 12 between memory 21 and microprocessor 8.
- the new firmware data to be loaded into memory 21 is then moved from the data port of the microprocessor (serial input or interface buffer) from memory 25 to the changeable portion of the flash memory, and the system waits for the flash memory to complete the 10m sec. programming time.
- the flash memory is preprogrammed with the BOOT code offline on a flash memory programmer and the programmed flash memory is then secured to a PCB along with microprocessor 8.
- FIG. 2 illustrates one typical organization of flash memory 21 including the preprogrammed portions or modules of firmware code.
- the first portion of memory 21 in FIG. 2 includes 12 bytes labeled “Vectors” and 65 bytes labeled “Startup.” These 77 bytes are preprogrammed into memory 21 as described above and their function is shown in the flow chart of FIG. 3.
- the microcontroller ports are initialized (block 101), the registers are cleared (block 102), the timers are initialized (block 103), and the serial input/output (SIO) baud rate clock is started (block 104).
- SIO serial input/output
- This clock is a serial baud generator which will recognize any input from the user and enable the SIO interrupt (block 105), followed by a predetermined time delay (block 106).
- the code for this power on/reset sequence is shown in pages 1 and 2 of the attached Appendix A.
- the next portion of memory 21 in FIG. 2 is labeled "Changeable Code” and represents 31,664 bytes which store the changeable firmware which can be addressed and modified by the user.
- the next preprogrammed portion of memory 21 that is utilized in the present invention is located at the high end of memory.
- the flash memory resides starting at address 000 and extending to address 7FFF, which is 32,000 bytes if it is converted from hex to decimal.
- the flash memory portion beginning at address 7C00 is firmware that is preprogrammed into the memory in addition to the preprogrammed Vectors and Startup portions discussed above.
- the first part of this portion is 17 bytes of code labeled "SIOINT" in FIG. 2 (block 111 in FIG. 4) that determines whether an interrupt that was generated from the serial port was a Control A character (block 112) which will place the system in this programming mode.
- the code for this routine is shown on page 3 of Appendix A.
- the system will go to the operation shown in the flow chart of FIG. 5, which is identified as the "Flash Utilities" (block 113) of 1024 bytes in FIG. 2 and which contains a number of routines.
- the system first displays a flash control message (block 121) for the user, these messages being "Verify Flash To SIO” (block 122), “SIO to Flash” (block 123) and “Reset” (block 124).
- the code for this display phase is shown on page 4 of Appendix A.
- "Verify Flash To SIO" code can, be downloaded from the serial port and checked to see if the code to be put into the changeable area of the flash memory is the same as the code already in the memory. This is useful because at times a user is not certain what revision level of code is in the memory.
- This utility compares every byte to be sent with each byte residing in the memory, based on the memory address, before it rewrites anything in the changeable code area. Referring to FIG. 6A, the flash memory is READ at the downloaded flash memory address (block 127) and a comparison made (block 128).
- the system will notify the user that there is a verified error at a specified address, that the byte it read and the byte that was to be sent to that address do not match. This is shown in FIG. 6A where the system sends a message "Verify Bad" (block 125) at the specified address if the compared bytes do not match.
- Utility number 3 "Reset" vectors the user back to, the start as a way to restart without turning power on and off again. This code for this procedure is shown at the top of page 6 of Appendix A.
- Utility number 2 "SIO to Flash" operates to move data from the serial port and write it into the free changeable code space in memory 21 based on the address provided by the user. This routine moves the data and handles all the re-programming of the flash memory.
- FIGS. 7, 8 and 9 show the steps executed when the user selects utility number 2. In FIG. 7, a message is displayed (block 131) telling the user he is waiting for a SYNC signal from the system. This is to insure synchronism with the system to enter the "Set Up DSP" phase (block 132).
- the system is instructed EXECUTE FROM INTERNAL DATA MEMORY; this means do not execute code from the external flash memory, but execute code from DSP RAM memory 22.
- the system waits for a line of data from the serial input (block 134). This allows the moving of a specified amount of data from RAM 25 of the microcontroller, preferably one line at a time, and writing it out to the changeable code portion of flash memory 21. If the transmitted line completes the requested loading (block 135), the system ends the flash loading (block 136). If there are more lines to be loaded, the system sets the user flag to show "one line present" (block 137) and proceeds to routine D in FIG. 8. The code for this phase of the operation is shown on page 7 of Appendix A.
- the flow chart of FIG. 8 of this routine includes obtaining the page address from registers R8 and R9 and the byte address within the addressed page from register R13 (block 141). After the first line is written, the system obtains the next line of code to be written and writes it to flash memory, repeating this until all writing is completed.
- flash memory architectures there are two different flash memory architectures available commercially; one is referred to as bulk erase, which means that to reprogram the flash memory, the command "Erase” is given.
- a difficulty with that architecture is that if the power goes off after such an erase, the entire flash memory contents are gone.
- the present invention uses a flash memory technology which allows erasing on a page basis as in the above-identified Atmel memory. In that flash memory, each page is 64 bytes, so that the present system is never sensitive to power outages.
- the system checks (block 142) to determine if the byte address and line length is greater than the size of a page of data that has already been loaded into RAM 25. If the new data involves a memory area which is larger than that loaded in RAM 25, it is desirable to load that portion which is already in RAM 25 into flash memory 21 before supplying the new data to RAM 25.
- FIG. 8 This is shown in FIG. 8 where the size of the code to be loaded is compared with a page size. If the comparison indicates an "equal to or greater than" condition (block 143), the page length is saved in register 4 (block 144) and the system proceeds with routine G shown in FIG. 9.
- the system determines (block 151) the number of bytes remaining on the present page and the number of bytes on the next page.
- the next step is to obtain a line of data from the serial port (SIO) (block 152) and load it into RAM 25 to complete a page of data in that RAM.
- This page of data is then programmed from RAM 25 to flash memory 21 (block 153) and the system then checks (block 154) to determine if there are additional bytes of code on the next page for that load. If so, the byte address in RAM 25 is set back to zero and the page address is advanced by one (block 155). The system then reads the next code into the newly designated page address and continues in this manner until all data has been written to memory 21.
- the system then proceeds to obtain the line check sum (block 156) which involves a known error detection technique in which a check sum of the bytes on each line of code downloaded from RAM 25 to memory 21 is obtained and compared with the number of bytes intended to be loaded. If the check sum indicates a proper byte count, the system returns by routine F to block 134 of FIG. 7 to wait for the next line of data from the serial port.
- the line check sum involves a known error detection technique in which a check sum of the bytes on each line of code downloaded from RAM 25 to memory 21 is obtained and compared with the number of bytes intended to be loaded. If the check sum indicates a proper byte count, the system returns by routine F to block 134 of FIG. 7 to wait for the next line of data from the serial port.
- the address When an address is downloaded, the address might not be an address that is on a page boundary. Thus, the system needs two parameters from the downloaded program; the page address, which one of the 512-pages, and which byte in that page is the writing to start on. If the system is downloading and it is not on a page boundary, the downloading could begin in the middle of a page and extend through another page. The present system detects an attempt to cross page boundaries and holds up further downloading, as shown in FIG. 10. When the system determines that it is over a page boundary, it must be prevented from sending additional data because the serial download is an asynchronous operation which is not clocked.
- an X-off character is sent to the system (block 162). This sets an internal code bit (block 163) telling the system to execute code out of the internal memory (blocks 164 and 165), dump the flash page, and switch back to non-extended timing (block 166). Then the internal code is disabled (block 171) and an X-on character is sent to the serial input (block 172), which tells the system to send additional code to the flash memory. This portion of the code is shown at the top of page 9 of Appendix A. ##SPC1##
Abstract
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US08/421,462 US5596738A (en) | 1992-01-31 | 1995-04-12 | Peripheral device control system using changeable firmware in a single flash memory |
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US82912992A | 1992-01-31 | 1992-01-31 | |
US08/421,462 US5596738A (en) | 1992-01-31 | 1995-04-12 | Peripheral device control system using changeable firmware in a single flash memory |
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