WO1995012853A1

WO1995012853A1 - A system and method for downloading digital data to remote passenger seat locations on an aircraft or other vehicle

Info

Publication number: WO1995012853A1
Application number: PCT/US1994/012523
Authority: WO
Inventors: John E. Lemmer; Paul A. Margis
Original assignee: Matsushita Avionics Development Corporation
Priority date: 1993-11-02
Filing date: 1994-11-01
Publication date: 1995-05-11
Also published as: AU8097594A

Abstract

A digital data distribution system (20) and method for sequentially transmitting digital data from a digital data storage unit to a plurality of remote passenger seat locations on a commercial aircraft or other vehicle. A plurality of digital data sequences are repeatedly and continuously broadcast over a digital data distribution system in a round robin fashion and remote digital data receiver units (30a-30n) are provided to store selected sequences of the data. In a preferred embodiment, the digital data storage unit comprises a game data storage unit or game downloader unit (10) of a video game system, and the remote receiver units comprise video game controller units. The game data storage unit includes a long term data storage device (44), such as a hard disk drive, a floppy disk drive (42) for entering video game data into the long term storage device, a system RAM (54) and a central processing unit (40).

Description

DESCRIPTION

A System and Method for Downloading Digital Data to Remote Passenger Seat Locations on an Aircraft or Other Vehicle

Field of the Invention

The field of the present invention is video game systems and data communication systems for use on commer¬ cial aircraft and other vehicles. Recently, substantial attention has been directed to the design and implementation of video game data transmis¬ sion systems for use on commercial aircraft and other vehicles. Such systems generally comprise a game data storage unit (or head end unit) , a data bus (or other data distribution system) , and a plurality of game controller units.

The game data storage unit generally includes a long term data storage device (for example, a conventional hard disk drive) , means for entering video game data into the data storage device (for example, a floppy disk drive) , a random access memory (RAM) , a central processing unit, a communications controller, and an interface circuit. In operation, video game data is loaded in a conventional fashion into the long term data storage device via the data entry means. Further, when access to the video game data is desired, the video game data is copied from the long term data storage device to the RAM under the control of the central processing unit. Once stored in the RAM, the video game data may be accessed by the communications controller and passed via the interface circuit to the data bus. The data bus, then, delivers the video game data to the game controller units .

Each game controller unit comprises an interface circuit, a random access memory (RAM) , a communications processor, and a game controller. The interface provides a communications link between the data bus and the commu¬ nications processor, and the communications processor stores selected data transmitted on the data bus in the RAM. Thereafter, the game controller may access video game data from the RAM and use that data to execute a video game program and display the video game on an associated video display unit.

Those skilled in the art will note that conventional video game systems of the type described above utilize a "command/response" protocol. For example, when a pass¬ enger at a given seat location desires to have a video game downloaded from the game data storage unit to his or her seat, the passenger must transmit a game request over a bus to the central processing unit of the game data storage unit . The request is stored in memory until acted upon (until all previous requests are processed) , and at that point the game selected by the passenger is passed down the data bus in the manner described above to the passenger's game controller unit.

While a command/response protocol may work well where only a few requests are processed simultaneously, such a protocol is nondeterministic and, thus, where many requests must be processed simultaneously, unacceptable delays are often introduced into the system. Moreover, because passengers must "take a number" and receive video game data in the order which requests are received, passengers are often forced to wait for several minutes before receiving the game data which they requested. On an airplane carrying between three and five hundred passengers, it is easy to see how substantial delays may be introduced into the game data distribution system. If a substantial number of passengers (for example, 100 passengers) request a given game, and later another passenger (or group of passengers) requests a second game, the passenger who requested the second game must wait for the first requested game to be transmitted as many as one hundred times before the second game may be transmitted. No doubt, there are a number of ways in which the efficiency of conventional game data distribution systems may be improved. For example, where a number of passen¬ gers have selected the same game, efficiency may be achieved by allowing all of those passengers to receive the selected game data simultaneously. This, however, will not assist the passengers or groups of passengers who have selected other games. The only option available to those passengers is to await the next transmission of the data corresponding to the game which they selected. Accordingly, those skilled in the art will appreciate that, where video game data must be provided to a large number of passengers, and where a substantial number of data requests may be made simultaneously or within a relatively short period of time, the average time required to download a given game (the "system download latency") may be substantial, on the order of several minutes.

Summary of the Invention

The present invention is directed to an improved system and method for downloading in a deterministic manner digital data from a digital data storage unit to a plurality of remote data receiver units. In one preferred embodiment, the digital data storage unit may comprise the head end unit of a video game system, and the remote data receiver units may comprise a plurality of video game controller units of that same system. For example, a video game system in accordance with the present invention may comprise a game downloader unit (GDLU) , a video signal distribution system, and a plurality of game data receiver units (GDRUs) .

In one particularly innovative aspect, the game downloader unit (GDLU) of the present invention continu¬ ously broadcasts video game data over the video signal distribution system in a "round robin" fashion. For example, where ten (10) games are stored in the game downloader unit (GDLU) , the game downloader unit will broadcast data corresponding to the first game (game 1) , followed by data corresponding to the second game (game 2) , and so on, until the data corresponding to the tenth game (game 10) has been transmitted over the video signal distribution system. After the transmission of game 10 the game downloader unit (GDLU) will again broadcast game 1. The game data receiver units (GDRUs) are configured, in turn, to programmably select only certain sequences of the data continuously broadcast by the game downloader unit (GDLU) (i.e. to select the data corresponding to one of the games) . In this fashion, the maximum download latency of a video game system in accordance with the present invention may be reduced essentially to the time required to trans¬ mit one full sequence of games (in the example above, the time required to transmit all ten games one time) . It follows that the "round robin" data transmission protocol of the present invention is highly deterministic and may be utilized to minimize the maximum download latency of a video game distribution systems .

In a preferred implementation, the data processing requirements in the game data receiver unit (GDRU) may be reduced by sequentially transmitting segments of the data corresponding to each of the stored video games rather than sequentially transmitting all of the data correspond¬ ing to each of the stored video games. It should be noted, however, that in this form the average download latency of the system will be slightly increased, due in part to the fact that at least one full transmission cycle will be required to download any game on the system, regardless of when the game is selected. In another particularly innovative aspect, the data broadcast by the game downloader unit (GDLU) may be properly formatted and distributed over a video signal distribution system already installed on an aircraft or other vehicle. This eliminates the need to utilize a dedicated game data transmission bus, and in doing so, reduces overall system costs and overall system weight . Accordingly, it is an object of the present invention to provide an improved digital data distribution system and method for use on commercial aircraft and other vehicles . It is a further object of the present invention to provide an improved video game data distribution system and method for use on commercial aircraft and other vehicles.

Brief Description of the Drawings Fig. 1 is a block diagram of a video game data distri¬ bution system in accordance with one form of the present invention.

Fig. 1(a) illustrates one data transmission format which may be utilized in accordance with the present invention.

Fig. 1(b) illustrates a second data transmission format which may be utilized in accordance with the present invention.

Fig. 1(c) illustrates the overall data transmission timing requirements if the digital data is carried within a conventional video signal .

Fig. 1(d) illustrates the organization of individual data packets within the active video interval of a conven¬ tional video signal. Fig. 2 is a block diagram representing the internal circuitry of a game downloader unit (GDLU) in accordance with a preferred form of the present invention.

Fig. 3 is a circuit diagram of a video data formatter in accordance with a preferred form of the present inven- tion.

Fig. 4 is a block diagram representing the internal circuitry of a game data receiver unit (GDRU) in accor¬ dance with a preferred form of the present.

Fig. 5 is a circuit diagram of a video decoder circuit in accordance with a preferred form of the present inven¬ tion. Detailed Description

Turning now to the drawings, Fig. 1 is a block diagram illustrating a digital data distribution system 1 in accordance with one form of the present invention. The digital data distribution system 1 may comprise, for example, a video game data distribution system for use on commercial aircraft and other vehicles. Accordingly, from this point on, the digital data distribution system 1 will be referred to as the video game data distribution system 1.

A video game data distribution system 1 in accordance with the present invention comprises a game downloader unit (GDLU) 10, a digital data distribution system 20 (for example, a data bus or a video signal distribution sys- tern) , and a plurality of digital data receiver units, referred to herein as game data receiver units (GDRUs) 30 (a) - (n) . The internal structure and configuration of the game downloader unit (GDLU) 10 and the game data receiver units (GDRUs) 30 (a) - (n) will be discussed in detail below. The digital data distribution system 20 may comprise either a conventional data bus or, in a particu¬ larly preferred form, a video signal distribution system already installed on an aircraft or other vehicle. An example of such a video signal distribution system is disclosed in U.S. Patent Application Serial No. 08/071,21- 8, filed June 1, 1993, a copy of which is attached hereto as Appendix A and is incorporated herein by reference.

As explained above, in a particularly innovative aspect of the present invention, video game data corre- sponding to a plurality of video games is continuously broadcast over the digital data distribution system 20 by the game downloader unit (GDLU) 10 in a "round robin" fashion.

In one form (particularly applicable where the digital data distribution system 20 comprises a dedicated data bus) , the video game data corresponding to each distinct video game is broadcast in a sequential manner and is preceded by a game address. More specifically, the data bytes 11 comprising a selected game program are preceded by a game address byte 13 and the game address and data bytes 11 and 13 are bounded by a pair of flag bytes 15. An example of this format is provided in Fig. 1(a) . The flag bytes 15 serve to identify the beginning and end of a data sequence, and the address byte 13 serves to identi¬ fy the programming data 11 broadcast within a given data sequence. Where ten (10) games are to be made available for use by passengers on a commercial aircraft, the game address 13 and program data 11 corresponding to the first game (game 1) will be broadcast over the digital data distribution system 20 and will be followed by the game address 13 and program data 11 corresponding to the second game (game 2) . Games 3-10 will then be broadcast over the digital data distribution system in a like manner. Upon the completion of the broadcast of game 10, game 1 will be broadcast again.

In another form (also particularly applicable to the dedicated bus implementation) , the data comprising each game program may be separated into a plurality of samples 17(a) -(j) comprising, for example, one byte or eight bits each. An example of this data format is provided in Fig. 1(b) . As shown in Fig. 1(b), a separate time slot or channel 17(a) -(j) (e.g. CHI-CHI0) within each frame is assigned to the program data of each game, and sequential data bytes are broadcast in sequential frames. Where all of the time slots assigned to a given game program are not utilized (i.e. where one game program is substantially shorter than the remaining game programs) , all unused time slots are filled with a flag sequence (not shown) indicat¬ ing the end of program data. It is preferred also to assign a frame address 19 to each frame of program data, such that when a data sample is received by a game data receiver unit GDRU 30, that data sample may be assigned a proper location within the memory of the game data receiv¬ er unit (GDRU) 30. This will enable the GDRUs 30 to begin storing selected program data as soon as a game program selection is made by a passenger or other system user.

In a presently preferred form, the video game data is broadcast in a format essentially identical to normal video signals. This format allows the sync clamping and white level clipping circuits in a radio frequency (RF) video modulator unit (VMU) , such as that described in U.S. Patent Application Serial No. 08/071,218, to operate normally with respect to maintaining maximum and minimum RF envelope characteristics and allows the automatic gain control (AGO circuits and automatic frequency control (AFC) circuits in a conventional video receiver to estab¬ lish the proper linear detection mode for received data. The overall timing requirements for the video format data signal are illustrated in Fig. 1(c) . The vertical blanking interval (VBI) 19 occupies 22 video line periods and conforms to conventional video signal requirements. The essential characteristics of the vertical blanking interval (VBI) 19 are well known in the art and, thus, need not be discussed in further detail herein. The active video interval (AVI) 21 occupies 240 video line periods and is used for transmitting the digital game data. The time periods shown in the figures are approxi¬ mate and correspond to a video line interval of 64 micro- seconds each.

The timing requirements of the data signal during the period corresponding to a normal video signal (the active video interval (AVI) 21 of Fig. 1(C)) are illustrated in Fig. 1(d) . The video signal segment 23, shown in Fig. 1(d) , is typical of each of the 240 lines occurring in the active video interval (AVI) 21 and represents a packet of data.

Each video signal segment depicted in Fig. 1(d) starts with a normal video NTSC sync pulse 25 consisting of a front porch 27, the actual sync signal 29, and a back porch 31. The characteristics of the video sync pulse 25 are well known in the art. The active data 33 to be transmitted follows the back porch 31 of the sync signal 25, and each packet of active data comprises a game identification bit group 35, a packet identification bit group 37, a plurality of game data bytes 39, and several error checking bits 41.

The game identification bit group 35 comprises a unique data sequence which identifies the game data transmitted in each data packet. The packet identifica¬ tion bit group 37 comprises a numeric value which identi- fies where a particular data packet for any specific game is to be placed in the game data receiver unit's (GDRU's) 30 memory. The game data bytes 39 comprise game program data, and the error checking bits 41 are used to check the accuracy of the data comprising the game data bytes 39. It can be recognized that, since each packet of data contains a game identifica ion bit group 35, sequential packets of data may comprise the program data of a single game or the program data of multiple games. The transmit- tal of sequential data packets which comprise the program data of a single game minimizes the average download latency of the system, however, specific game download latencies will vary in duration from a very short period of time (the time required to transmit a single game) to the time required to transmit each game once. On the other hand, if sequential data packets comprise the program data of sequential games, the system download latency will be the same for all events.

Those skilled in the art will appreciate that by utilizing the round robin data transmission protocol of the present invention, the maximum download latency of the video game system 1 may be minimized. Thus, the excessive download latency which may potentially arise in systems using a command/response protocol is avoided.

Each game data receiver unit (GDRU) 30(a) - 30 (n) is capable of programmably selecting certain sequences of data from the continuous stream of data broadcast over the digital data distribution system 20. For example, each game data receiver unit (GDRU) 30(a) may be programmed to receive only data corresponding to the first game (game 1) in the sequence of continuously transmitted game data. Further, depending upon the game data transmission format utilized, the game data receiver unit (GDRU) 30 may be configured to identify game data corresponding to a selected game and to store in memory only those data bytes associated with the selected game. Those skilled in the art will note that the game data formats discussed above are exemplary, and that numerous other formats may be utilized in a game data distribution system in accordance with the present invention.

Turning now also to Fig. 2, a game downloader unit (GDLU) 10 in accordance with the present invention may comprise, for example, a microprocessor 40, a floppy disk drive 42, a long term data storage device 44 (for example, a hard disk drive) , a direct memory access device 46, a data packet formatter (DPF) 48, a serial communications controller 50, a video data formatter (VDF) 52, a plurali- ty of system memory circuits 54 (including at least one RAM not shown) , and a data bus 56.

The floppy disk drive 42 provides a means for entering video game program data into the long term data storage device 44 of the game downloader unit (GDLU) 10. Data transfers between and among the various components com¬ prising the game downloader unit (GDLU) 10 are controlled, for the most part, by the microprocessor 40. However, when selected program data is to be broadcast by the game downloader unit (GDLU) 10, the following routine is implemented. The data to be broadcast is transferred from the long term data storage device 44 to the RAM of the system memory 54 under the control of the microprocessor 40. Once the selected data is received by the RAM of the system memory 54, it may be accessed by the direct memory access (DMA) circuit 46. More specifically, the direct memory access (DMA) circuit 46 points to selected data stored in the RAM of the system memory 54, and the select- ed data is then transferred directly from the RAM of the system memory 54 through the direct memory access (DMA) circuit 46 to the data packet formatter (DPF) 48. The data packet formatter (DPF) 48 receives clock 58 and synchronization 60 signals from the video data formatter (VDF) 52 and, in response, provides a serial data stream 62 comprising the data accessed from the system memory 54 to the video data formatter (VDF) 52. More specifically, the data packet formatter (DPF) 48 receives data from the direct memory access (DMA) circuit 46 and formats that data (adds clocking, synchronization signals, and framing to the received data) to form a synchronous bit stream which may be processed by the video data formatter (VDF) 52. In a preferred form, the video data formatter (VDF) 52 takes the bit stream received from the data packet formatter (DPF) 48 and transforms that bit stream into a standard video format. More specifically, the video data formatter (VDF) 52 insures that each data packet (illus¬ trated in Fig. 1(d)) is placed within successive horizon- tal sync pulses conforming to conventional video signal requirements.

A circuit diagram of a video data formatter (VDF) 52 in accordance with the present invention is provided in Fig. 3. As shown, the video data formatter 52 comprises a clock crystal 70, a video sync generator 72, and a video signal generation circuit 74. The clock crystal 70 provides a stable clock signal to the video sync generator 72, and in response to the received clock signal, the video sync generator 72 provides clock and data sync signals to the data packet formatter (DPF) 48 and the video signal generation circuit 74. The data packet formatter (DPF) 48 utilizes the clock and data sync signals received from the video sync generator 72 to format the data received from the RAM of the system memory 54. The formatted data is then provided to the video signal generation circuit 74 for conversion to the video format . The video signal produced by the video signal generation circuit 74 is provided to the video signal distribution system 20 and may be broadcast at baseband or modulated on a carrier frequency for transmission to the game data receiver units (GDRUs) 30. Turning now to Fig. 4, a game data receiver unit (GDRU) 30 in accordance with a preferred form of the present invention may comprise a video tuner 80, a tuner control 82, a video decoder circuit 84, a data packet receiver circuit 86, a direct memory access 88, a random access memory 90, and a game processor unit 92.

Where the video game data is converted to a conven¬ tional video signal and modulated on a carrier frequency in a conventional fashion, each game data receiver unit 30 will comprise (or will be coupled to) a RF video tuner 80. The RF tuner 80 is coupled to and controlled by a tuner control circuit 82, and in response to electrical signals provided to it by the tuner control circuit 82, the RF tuner 80 may select a video signal for transmission to the video decoder circuit 84. Those skilled in the art will also note that where both game data and true video signals are broadcast over the video signal distribution system, it is advantageous to allow the tuner control circuit 82 to control a switch 94, such that true video signals may be provided directly to a video display (not shown) and such that video signals comprising game data may be provided to the video decoder circuit 84.

Upon receiving a video signal from the RF tuner 80, the video decoder circuit 84 separates the received video signal to form three signals (sync, data, and clock) , which are in turn provided to the data packet receiver circuit 86. The data packet receiver circuit then deliv¬ ers the sync, data, and clock signals to the direct memory access circuit 88, and the direct memory access circuit 88 causes the received data to be stored in the RAM 90 for use by the game processor 92. Those skilled in the art will appreciate that the game processor 92 may comprise any conventional game processor, and that the RAM 90 merely performs the function of a conventional game card memory.

Turning now to Fig. 5, the video decoder circuit 84 may comprise, for example, a sync separator 96 (for example, an Elantec EL 4581) , a DC restorer circuit 98

(for example, an Elantec EL 2090CN) , a data comparator circuit 100 (for example, a Linear Technologies LT1016) , and a clock recovery circuit 102 (for example, an AT&T

T7032) . All of the components listed in the previous sentence are conventional ("off the shelf") components, and thus, only the general function of those components is described below.

The sync separator 96 extracts vertical and horizontal sync information from the received signal and provides that information to the data packet receiver circuit 86. The sync separator 96 also provides a pulse during the back porch portion of the received signal to the DC restorer circuit 98.

The DC restorer circuit 98 uses the back porch pulse from the sync separator 96 to establish the back porch level of the signal from the DC restorer circuit 98 at 0 volts or ground. The signal levels corresponding to the data 1 and data 0 states are set to pre-determined voltag¬ es above ground. The data comparator circuit 100, in turn, converts the DC restored video signal to a digital data bit stream (i.e. a sequence of "Is" and "0s") , and provides the digital data bit stream to the clock recovery circuit 102. The clock recovery circuit 102 recovers the data transmis- sion frequency (or clocking) from the digital data bit stream and provides both a clock signal and the digital data bit stream to the packet formatter circuit 86.

Turning again to Fig. 4, the data packer receiver circuit 86 uses the vertical and horizontal sync pulses from the sync separator circuit 96 and the clock and data signals from the clock recovery circuit 102 to form address and data bytes for use by the direct memory access circuit 88. Those skilled in the art will appreciate that the address bytes indicate where the data bytes are to be stored in the RAM 90.

Once the data comprising a video game has been stored in the RAM 92, that data may be accessed by the game processor 92, and the instructions contained in that data may be executed in a conventional fashion. As set forth above, the game processor 92 may comprise virtually any game processor. While the present invention is susceptible to various modifications and alternative forms, specific representa¬ tions and illustrations thereof have been shown, by way of example, in the drawings and are herein described in detail. It should be understood, however, that it is not intended to limit the invention to the particular systems and methods disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alterna¬ tives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

Claims:

1. A method for transmitting a plurality of data sequences stored in a long term memory device to a plural¬ ity remote passenger seat locations in a commercial aircraft or other vehicle, said method comprising the steps of : transferring said data sequences from said long term memory device to a local memory (RAM) ; sequentially and repetitively accessing each of said plurality of data sequences using a direct memory access device; transmitting each of said accessed data sequences over a signal distribution system such that said data sequences are continuously transmitted over said signal distribution system in a round robin fashion; and selectively receiving and storing in a memory at a remote passenger seat location a single data sequence of said plurality of transmitted data sequences.

2. A digital data transmission system for use on commercial aircraft and other vehicles, said digital data transmission system comprising: a digital data download unit for sequentially and repetitively transmitting a plurality of digital data sequences over a digital signal distribution network in a round robin fashion; and a digital data receiver unit for selecting one digital data sequence from said plurality of transmitted digital data sequences and storing said selected digital data sequence in a memory.

3. The digital data transmission system of claim 2 wherein said digital signal distribution network comprises a video signal distribution network capable of installa¬ tion on an aircraft or other vehicle.

4. A video game downloader unit for use on commer¬ cial aircraft and other vehicles comprising: a long term data storage device for storing digital video game data; a floppy disk drive for receiving and transferring said digital video game data to said long term data storage device; a system memory circuit for receiving said digital video game data from said long term data storage device and storing said digital video game data prior to and during a video data transmission sequence; a microprocessor for controlling a transfer of said digital video game data from said long term data storage device to said system memory circuit; a direct memory access circuit for repeatedly access¬ ing selected sequences of said digital video game data stored within said system memory circuit such that said selected sequences of said digital video game data are repeatedly provided to a data transmission network in a round robin fashion.