WO1996026519A1 - Synchronous srams having logic for memory expansion - Google Patents

Synchronous srams having logic for memory expansion Download PDF

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Publication number
WO1996026519A1
WO1996026519A1 PCT/US1996/002023 US9602023W WO9626519A1 WO 1996026519 A1 WO1996026519 A1 WO 1996026519A1 US 9602023 W US9602023 W US 9602023W WO 9626519 A1 WO9626519 A1 WO 9626519A1
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WIPO (PCT)
Prior art keywords
sram
chip enable
enable
coupled
synchronous
Prior art date
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PCT/US1996/002023
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French (fr)
Inventor
Joseph Thomas Pawlowski
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Micron Technology, Inc.
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Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Publication of WO1996026519A1 publication Critical patent/WO1996026519A1/en
Priority to US09/861,838 priority Critical patent/US6531465B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • This invention relates to synchronous SRAMs (Static Random Access Memories).
  • Synchronous SRAMs are a type of SRAM that is registered and accessed in accordance with externally generated clock signals.
  • the clock signal provides for synchronous operation of the SRAM.
  • memory devices commonly increase in size by a factor of four from one generation to the next.
  • the next generation memory device after a 256K bit memory device is a 1 M bit device.
  • the 4M device is the 4M device, and so on.
  • This fourfold generational jump in memory size leaves a significant gap in memory depth between generation sizes. For example, suppose that a 32Kx36 memory device and a 128Kx36 memory device are available, but a designer wants to implement an intermediate memory size, such as a 64Kx36 memory device.
  • the ability to achieve intermediate memory sizes is desirable because it affords system design flexibility without the drawback of over or under utilizing memory capacity.
  • One common technique for achieving memory depth expansion is by stacking two or more memory devices together and adding external logic to control them. This is not a favorable alternative, however, because it complicates system level design. It is more desirable to provide the intermediate memory device size without introducing external logic.
  • Synchronous burst SRAMs have an internal counter which facilitates internal addressing of typically two to four addresses for each externally generated address that is loaded into the memory device.
  • the internal "burst" addresses can be generated more rapidly in comparison to externally generating the same addresses and then loading them into the memory device using conventional techniques. Accordingly, the burst SRAMs operate faster and achieve higher performance.
  • synchronous burst SRAMs it is desirable and advantageous for synchronous burst SRAMs to facilitate a microprocessor-related function known as "address pipelining".
  • a microprocessor attached to the synchronous burst SRAM outputs an address and data strobe signal each time a new address is ready for input into the SRAM device.
  • it may be desirable to delay execution of that new address For example, in a synchronous burst SRAM, it might be desirable to continue the burst addressing operation before accepting the next external address.
  • the synchronous burst SRAMs must be capable of blocking or delaying operation on the new address (as indicated by the address and data strobe signal from the microprocessor) until the burst operation is completed.
  • a synchronous SRAM module comprises a first SRAM unit having a memory array and control circuitry for accessing the memory array, the first SRAM unit having first, second, and third chip enable inputs, a second SRAM unit having a memory array and control circuitry for accessing the memory array, the second SRAM unit having first, second, and third chip enable inputs.
  • the synchronous SRAM module further comprises a module enable and memory selection circuit operably coupled to selectively enable or disable both SRAM units and to choose one of the first and second SRAM units for access, the memory module enable and memory selection circuit generating a module enable signal and a memory select enable signal.
  • the memory select enable signal being coupled to at least one of the first and second chip enable inputs of the first and second SRAM units for selecting the first SRAM unit when the memory select enable signal is at one asserted logic level and for selecting the second SRAM unit when the memory select enable signal is at another asserted logic level.
  • the module enable signal being coupled to the third chip enable inputs of the first and second SRAM units for enabling operation of both SRAM units when the module enable signal is at one asserted logic level and for disabling operation of both SRAM units when the module enable signal is at another asserted logic level.
  • a synchronous burst SRAM devices comprises an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers, an address register for receiving addresses for the memory array in the SRAM core, a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register.
  • the synchronous burst SRAM module further comprises an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register, three chip enable inputs for receiving chip enable signals, and chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of ( 1 ) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean function of the chip enable signals.
  • the synchronous SRAM module also includes an enable register coupled between the chip enable and select logic and the SRAM core for temporarily storing the SRAM core enable signal, and pipelining logic coupled to at least one of the three chip enable inputs to block the external address signal when one chip enable signal received at the one chip enable input is at a selected asserted logic level to thereby permit pipelining operation of the synchronous burst SRAM device.
  • FIG. 1 illustrates a block diagram of a synchronous SRAM module constructed according to this invention
  • Fig. 2 illustrates a detailed block diagram of a synchronous burst SRAM device according to this invention.
  • FIG. 1 illustrates a synchronous SRAM module 10 designed to provide an intermediate-sized memory device.
  • SRAM module 10 includes a first SRAM unit 12 of a common memory size and a second SRAM unit 14 of a common memory size which are stacked together to effectively double the memory capacity.
  • first SRAM unit 12 and second SRAM unit 14 might both be 32Kx36 synchronous SRAMs.
  • the first and second SRAM units form a 64Kx36 synchronous SRAM module.
  • Both the first and second SRAM units comprise a memory array and control circuitry for accessing the memory array.
  • One preferred embodiment of an SRAM unit is a synchronous burst SRAM device described below in more detail with reference to Fig. 2.
  • Each of the SRAM units 12 and 14 are equipped with three chip enable inputs.
  • the three chip enable inputs are advantageous over prior art designs in that they serve the dual tasks of permitting selection of either the first SRAM unit 12 or the second SRAM unit 14, while also providing a means for powering down or disabling both SRAM units simultaneously.
  • both SRAM units 12 and 14 have a first chip enable input /CE2, a second chip enable input CE2, and a third chip enable input /CE.
  • the first chip enable input /CE2 of first SRAM unit 12 and the second chip enable input CE2 of second SRAM unit 14 are tied together to receive a memory select enable signal over conductor 16.
  • the second chip enable input of first SRAM unit 12 is coupled to power V cc and the first chip enable input of second SRAM unit 14 is coupled to ground G ND .
  • the memory select enable signal applied over conductor 16 operably chooses between the first SRAM unit 12 and the second SRAM unit 14 according to the asserted logic level of the signal.
  • the memory select enable signal is at one asserted logic level, such as asserted LOW
  • first SRAM unit 12 is chosen.
  • second SRAM unit 14 is selected when the memory select enable signal is at another asserted logic level, such as asserted HIGH.
  • the memory select enable signal is a bit in an address used to access the memory array in the first or second SRAM units. As illustrated in Fig. 1. the most significant bit (MSB) A15 is used as the memory select enable signal to operably choose between the first SRAM unit 12 and the second SRAM unit 14.
  • MSB most significant bit
  • a module enable signal /CE is coupled via conductor 18 to the third chip enable input /CE of the first and second SRAM units 12 and 14.
  • the module enable signal enables operation of both SRAM units when the signal is at one asserted logic level, such as asserted LOW, and disables operation of both SRAM units when the module enable signal is at another asserted logic level, such as asserted HIGH.
  • Memory module 10 of this invention is therefore advantageous over prior art designs in that it permits the entire module (comprising multiple SRAM units) to be completely powered down.
  • the illustrated coupling arrangement for stacking first and second SRAM units 12 and 14 is one preferred construction of a module enable and memory selection circuit 20 which in part controls operation of the synchronous SRAM module 10. It should be noted that other coupling arrangements defining circuit 20 can be used.
  • conductor 16 can be coupled to the second chip enable input CE2 of first SRAM unit 12 and to first chip enable input /CE2 of second SRAM unit 14.
  • first chip enable input /CE2 of first SRAM unit 12 would be connected to ground and the second chip enable input CE2 of second SRAM unit 14 would be connected to power.
  • Fig. 2 shows a preferred construction of a synchronous burst SRAM device 30 which can be incorporated as one of the SRAM units 12 and 14 in SRAM module 10.
  • Synchronous burst SRAM device 30 includes an SRAM core 32 of conventional construction.
  • Synchronous SRAM core 32 includes a memory array 34, one or more write drivers 36 for temporarily holding data for input into the memory array 34, sense amplifiers 38, and I/O buffers 40 (such as input registers IR and output buffers OB and optionally output registers) to facilitate transfer of data to and from the memory array.
  • write drivers 36 for temporarily holding data for input into the memory array 34
  • sense amplifiers 38 for temporarily holding data for input into the memory array 34
  • I/O buffers 40 such as input registers IR and output buffers OB and optionally output registers
  • Address control circuitry 42 is coupled to SRAM core 32 for accessing a selected location in the memory array within the SRAM core.
  • address control circuitry 42 comprises an address register 44 for receiving externally generated addresses A0-A14 and a burst address generator 46 coupled to the address register 44.
  • the burst address generator 46 rapidly generates additional internal addresses using at least one. and preferably two or more, address bits stored in the address register.
  • burst address generator 46 comprises a two bit binary counter which employs the two least significant bits (LSB) A0 and Al to generate additional addresses internally at a much higher rate as compared to external generation of the same addresses.
  • Synchronous burst SRAM device 30 has multiple one-bit write registers 48 which activate corresponding write drivers 36 to input data into the memory array during a write operation.
  • write registers 48 hold one binary bit. such as a “1 ". write drivers 36 are enabled to transfer data to memory array 34; whereas, when write registers 48 hold the other binary bit, such as a "0", the write drivers are not enabled indicating that a read operation is being performed.
  • the write registers 48 are controlled by respective bit write signals /BW1 , BW2, /BW3, and /BW4 and a clock input signal CLK.
  • the operation of write registers 48 is also partially controlled by the logical combination of the module enable signal /CE and an external address signal /ADSP.
  • the external address signal is in the form of an address and data strobe from the microprocessor /ADSP which indicates that an external address is ready to be loaded into address register 44.
  • the remaining inputs to the SRAM device 30 include: an address advance signal input /ADV which is used to increment the binary counter in the burst address generator 46; an input to receive the address and strobe signal from the controller /ADSC; the three chip enable inputs /CE2, CE2, and /CE; an output enable input /OE input; and optionally a parity disable PDIS input.
  • the three chip enable inputs are the same as those described above with reference to Fig. 1.
  • synchronous burst SRAM device 30 is used as the first SRAM unit 12 in the SRAM module 10 of Fig. 1.
  • the first chip enable input /CE2 (referenced by numeral 50) is coupled to receive the MSB A15
  • the second chip enable input CE2 (referenced by numeral 52) is tied to power V cc
  • the third chip enable input /CE (referenced by numeral 54) is connected to receive the module enable signal.
  • Synchronous burst SRAM device 30 also includes chip enable and select logic 56 coupled to the three chip enable inputs 50, 52. and 54.
  • the chip enable and select logic 56 performs the dual functions of (1) selectively enabling or disabling the synchronous burst SRAM device, and (2) selectively permitting access to the SRAM core 32 when the SRAM device is enabled. These functions are achieved based upon a boolean function of the signals at the three chip enable inputs.
  • the chip enable and select logic 56 generates an SRAM core enable signal for enabling SRAM core 32 as a result of the boolean function provided by logic 56.
  • a one-bit enable register 58 is coupled between the chip enable and select logic 56 and the SRAM core 32 for temporarily storing the SRAM core enable signal. In this manner, the SRAM core is merely responsive to a single enable signal held in register 58, although this single core enable signal is generated according to a relationship among the three chip enable signals to the entire SRAM device.
  • chip enable and select logic 56 comprises a AND gate 60 having three inputs coupled to the three chip enable inputs 50, 52, 54 and an output coupled to enable register 58.
  • the boolean function for combining the three chip enable signals /CE, /CE2, CE2 is defined as: /CE AND /CE2 AND CE2.
  • SRAM device 30 also includes address pipelining logic 62 which is coupled to at least one of the three chip enable inputs, and more specifically, to the third chip enable input 54.
  • Pipelining logic 62 is provided to block the external address signal /ADSP from notifying the chip that an external address is waiting to be loaded into the address register. This signal blocking function permits the synchronous burst SRAM device to operate in a pipelining mode. An example operation in the pipelining mode is to allow the burst address generator 46 to generate multiple additional addresses without interference from an external address as indicated by the external address signal /ADSP.
  • the pipelining logic 62 comprises a NOR gate having one input tied to the microprocessor produced address and data strobe /ADSP and one input coupled to the module enable signal at third chip enable input 54. In this manner, when the module enable signal at input 54 is at a selected asserted logic level, such as asserted HIGH, pipelining logic 62 blocks the external address signal /ADSP from affecting operation of the SRAM device to thereby permit pipelining operation.
  • enable register 58, and pipelining logic 62 thereby provide device control circuitry for performing three desired functions: (1 ) selectively enabling or disabling the SRAM device, (2) , selectively permitting access to the SRAM core when the SRAM device is enabled, and (3) selectively permitting pipelining operation of the SRAM device.
  • the circuitry arrangement of this invention achieves these desired features without introducing additional external logic or circuitry. Additionally, this invention accomplishes these desired results through the use of inexpensive logic design comprised of a few logical gates and registers. The invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect.

Abstract

A synchronous SRAM module comprises first and second SRAM chips. Each SRAM chip has three chip enable inputs. A module enable and memory selection circuit is coupled to the two SRAM chips to perform the dual tasks of (1) selectively enabling or disabling both SRAM chips and (2) choosing either the first or second SRAM chips for access. The SRAM module can also be placed in a pipelining mode where external signals from a microprocessor are ignored to facilitate internal operation, such as burst reads. A synchronous burst SRAM device employed in the SRAM module is also described.

Description

SYNCHRONOUS SRAMS HAVING LOGIC FOR MEMORY EXPANSION
Technical Field of the Invention This invention relates to synchronous SRAMs (Static Random Access Memories).
Background of the Invention Synchronous SRAMs are a type of SRAM that is registered and accessed in accordance with externally generated clock signals. The clock signal provides for synchronous operation of the SRAM.
In memory design evolution, memory devices commonly increase in size by a factor of four from one generation to the next. For example, the next generation memory device after a 256K bit memory device is a 1 M bit device. Following the IM device is the 4M device, and so on. This fourfold generational jump in memory size leaves a significant gap in memory depth between generation sizes. For example, suppose that a 32Kx36 memory device and a 128Kx36 memory device are available, but a designer wants to implement an intermediate memory size, such as a 64Kx36 memory device. The ability to achieve intermediate memory sizes is desirable because it affords system design flexibility without the drawback of over or under utilizing memory capacity.
One common technique for achieving memory depth expansion is by stacking two or more memory devices together and adding external logic to control them. This is not a favorable alternative, however, because it complicates system level design. It is more desirable to provide the intermediate memory device size without introducing external logic.
To avoid the use of external logic, another prior art approach employs two separate SRAM devices, where each device is equipped with an active low and an active high chip enable. The two chip enables are internally logically combined so that one signal is used to selectively access one of the two synchronous SRAMs. One of the drawbacks in this design, however, is that there is no ability to operably disable both devices simultaneously or operate the devices in a pipelining mode (discussed below).
One specific type of synchronous SRAMs is a synchronous burst SRAM which is designed in systems to achieve higher SRAM performance. Synchronous burst SRAMs have an internal counter which facilitates internal addressing of typically two to four addresses for each externally generated address that is loaded into the memory device. The internal "burst" addresses can be generated more rapidly in comparison to externally generating the same addresses and then loading them into the memory device using conventional techniques. Accordingly, the burst SRAMs operate faster and achieve higher performance.
It is desirable and advantageous for synchronous burst SRAMs to facilitate a microprocessor-related function known as "address pipelining". In general, a microprocessor attached to the synchronous burst SRAM outputs an address and data strobe signal each time a new address is ready for input into the SRAM device. On occasions, it may be desirable to delay execution of that new address. For example, in a synchronous burst SRAM, it might be desirable to continue the burst addressing operation before accepting the next external address. Accordingly, the synchronous burst SRAMs must be capable of blocking or delaying operation on the new address (as indicated by the address and data strobe signal from the microprocessor) until the burst operation is completed.
It is also worth noting that achieving intermediate sizes in memories can be costly. The economies are best realized through the fourfold generational size increase. There is a continuing need to design intermediate memory sizes that are also inexpensive to manufacture.
The synchronous SRAM of this invention overcomes the above drawbacks by providing an intermediate memory depth without use of external logic. The novel synchronous SRAM also includes a pipelining mode and a power down mode without expensive components or circuitry. Summary of the Invention According to one aspect of this invention, a synchronous SRAM module comprises a first SRAM unit having a memory array and control circuitry for accessing the memory array, the first SRAM unit having first, second, and third chip enable inputs, a second SRAM unit having a memory array and control circuitry for accessing the memory array, the second SRAM unit having first, second, and third chip enable inputs. The synchronous SRAM module further comprises a module enable and memory selection circuit operably coupled to selectively enable or disable both SRAM units and to choose one of the first and second SRAM units for access, the memory module enable and memory selection circuit generating a module enable signal and a memory select enable signal. The memory select enable signal being coupled to at least one of the first and second chip enable inputs of the first and second SRAM units for selecting the first SRAM unit when the memory select enable signal is at one asserted logic level and for selecting the second SRAM unit when the memory select enable signal is at another asserted logic level. The module enable signal being coupled to the third chip enable inputs of the first and second SRAM units for enabling operation of both SRAM units when the module enable signal is at one asserted logic level and for disabling operation of both SRAM units when the module enable signal is at another asserted logic level.
According to another aspect of this invention, a synchronous burst SRAM devices comprises an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers, an address register for receiving addresses for the memory array in the SRAM core, a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register. The synchronous burst SRAM module further comprises an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register, three chip enable inputs for receiving chip enable signals, and chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of ( 1 ) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean function of the chip enable signals. The synchronous SRAM module also includes an enable register coupled between the chip enable and select logic and the SRAM core for temporarily storing the SRAM core enable signal, and pipelining logic coupled to at least one of the three chip enable inputs to block the external address signal when one chip enable signal received at the one chip enable input is at a selected asserted logic level to thereby permit pipelining operation of the synchronous burst SRAM device.
Brief Description of the Drawings Fig. 1 illustrates a block diagram of a synchronous SRAM module constructed according to this invention; and
Fig. 2 illustrates a detailed block diagram of a synchronous burst SRAM device according to this invention.
Detailed Description of the Invention Fig. 1 illustrates a synchronous SRAM module 10 designed to provide an intermediate-sized memory device. SRAM module 10 includes a first SRAM unit 12 of a common memory size and a second SRAM unit 14 of a common memory size which are stacked together to effectively double the memory capacity. For example, first SRAM unit 12 and second SRAM unit 14 might both be 32Kx36 synchronous SRAMs. When coupled together according to this invention, the first and second SRAM units form a 64Kx36 synchronous SRAM module.
Both the first and second SRAM units comprise a memory array and control circuitry for accessing the memory array. One preferred embodiment of an SRAM unit is a synchronous burst SRAM device described below in more detail with reference to Fig. 2.
Each of the SRAM units 12 and 14 are equipped with three chip enable inputs. The three chip enable inputs are advantageous over prior art designs in that they serve the dual tasks of permitting selection of either the first SRAM unit 12 or the second SRAM unit 14, while also providing a means for powering down or disabling both SRAM units simultaneously. More particularly, both SRAM units 12 and 14 have a first chip enable input /CE2, a second chip enable input CE2, and a third chip enable input /CE. The first chip enable input /CE2 of first SRAM unit 12 and the second chip enable input CE2 of second SRAM unit 14 are tied together to receive a memory select enable signal over conductor 16. The second chip enable input of first SRAM unit 12 is coupled to power Vcc and the first chip enable input of second SRAM unit 14 is coupled to ground GND.
According to this circuit construction, the memory select enable signal applied over conductor 16 operably chooses between the first SRAM unit 12 and the second SRAM unit 14 according to the asserted logic level of the signal. When the memory select enable signal is at one asserted logic level, such as asserted LOW, first SRAM unit 12 is chosen. Conversely, second SRAM unit 14 is selected when the memory select enable signal is at another asserted logic level, such as asserted HIGH. In the preferred embodiment, the memory select enable signal is a bit in an address used to access the memory array in the first or second SRAM units. As illustrated in Fig. 1. the most significant bit (MSB) A15 is used as the memory select enable signal to operably choose between the first SRAM unit 12 and the second SRAM unit 14.
A module enable signal /CE is coupled via conductor 18 to the third chip enable input /CE of the first and second SRAM units 12 and 14. The module enable signal enables operation of both SRAM units when the signal is at one asserted logic level, such as asserted LOW, and disables operation of both SRAM units when the module enable signal is at another asserted logic level, such as asserted HIGH. Memory module 10 of this invention is therefore advantageous over prior art designs in that it permits the entire module (comprising multiple SRAM units) to be completely powered down. The illustrated coupling arrangement for stacking first and second SRAM units 12 and 14 is one preferred construction of a module enable and memory selection circuit 20 which in part controls operation of the synchronous SRAM module 10. It should be noted that other coupling arrangements defining circuit 20 can be used. For example, conductor 16 can be coupled to the second chip enable input CE2 of first SRAM unit 12 and to first chip enable input /CE2 of second SRAM unit 14. In this alternative construction, the first chip enable input /CE2 of first SRAM unit 12 would be connected to ground and the second chip enable input CE2 of second SRAM unit 14 would be connected to power. Fig. 2 shows a preferred construction of a synchronous burst SRAM device 30 which can be incorporated as one of the SRAM units 12 and 14 in SRAM module 10. Synchronous burst SRAM device 30 includes an SRAM core 32 of conventional construction. Synchronous SRAM core 32 includes a memory array 34, one or more write drivers 36 for temporarily holding data for input into the memory array 34, sense amplifiers 38, and I/O buffers 40 (such as input registers IR and output buffers OB and optionally output registers) to facilitate transfer of data to and from the memory array.
Address control circuitry 42 is coupled to SRAM core 32 for accessing a selected location in the memory array within the SRAM core. Preferably, address control circuitry 42 comprises an address register 44 for receiving externally generated addresses A0-A14 and a burst address generator 46 coupled to the address register 44. The burst address generator 46 rapidly generates additional internal addresses using at least one. and preferably two or more, address bits stored in the address register. In this construction, burst address generator 46 comprises a two bit binary counter which employs the two least significant bits (LSB) A0 and Al to generate additional addresses internally at a much higher rate as compared to external generation of the same addresses.
Synchronous burst SRAM device 30 has multiple one-bit write registers 48 which activate corresponding write drivers 36 to input data into the memory array during a write operation. When write registers 48 hold one binary bit. such as a "1 ". write drivers 36 are enabled to transfer data to memory array 34; whereas, when write registers 48 hold the other binary bit, such as a "0", the write drivers are not enabled indicating that a read operation is being performed. The write registers 48 are controlled by respective bit write signals /BW1 , BW2, /BW3, and /BW4 and a clock input signal CLK. The operation of write registers 48 is also partially controlled by the logical combination of the module enable signal /CE and an external address signal /ADSP. In this embodiment, the external address signal is in the form of an address and data strobe from the microprocessor /ADSP which indicates that an external address is ready to be loaded into address register 44. The remaining inputs to the SRAM device 30 include: an address advance signal input /ADV which is used to increment the binary counter in the burst address generator 46; an input to receive the address and strobe signal from the controller /ADSC; the three chip enable inputs /CE2, CE2, and /CE; an output enable input /OE input; and optionally a parity disable PDIS input.
The three chip enable inputs are the same as those described above with reference to Fig. 1. For purposes of continuing discussion, assume that synchronous burst SRAM device 30 is used as the first SRAM unit 12 in the SRAM module 10 of Fig. 1. As shown in Fig. 1 , the first chip enable input /CE2 (referenced by numeral 50) is coupled to receive the MSB A15, the second chip enable input CE2 (referenced by numeral 52) is tied to power Vcc, and the third chip enable input /CE (referenced by numeral 54) is connected to receive the module enable signal.
Synchronous burst SRAM device 30 also includes chip enable and select logic 56 coupled to the three chip enable inputs 50, 52. and 54. The chip enable and select logic 56 performs the dual functions of (1) selectively enabling or disabling the synchronous burst SRAM device, and (2) selectively permitting access to the SRAM core 32 when the SRAM device is enabled. These functions are achieved based upon a boolean function of the signals at the three chip enable inputs. The chip enable and select logic 56 generates an SRAM core enable signal for enabling SRAM core 32 as a result of the boolean function provided by logic 56. A one-bit enable register 58 is coupled between the chip enable and select logic 56 and the SRAM core 32 for temporarily storing the SRAM core enable signal. In this manner, the SRAM core is merely responsive to a single enable signal held in register 58, although this single core enable signal is generated according to a relationship among the three chip enable signals to the entire SRAM device.
In the preferred form, chip enable and select logic 56 comprises a AND gate 60 having three inputs coupled to the three chip enable inputs 50, 52, 54 and an output coupled to enable register 58. The boolean function for combining the three chip enable signals /CE, /CE2, CE2 is defined as: /CE AND /CE2 AND CE2.
SRAM device 30 also includes address pipelining logic 62 which is coupled to at least one of the three chip enable inputs, and more specifically, to the third chip enable input 54. Pipelining logic 62 is provided to block the external address signal /ADSP from notifying the chip that an external address is waiting to be loaded into the address register. This signal blocking function permits the synchronous burst SRAM device to operate in a pipelining mode. An example operation in the pipelining mode is to allow the burst address generator 46 to generate multiple additional addresses without interference from an external address as indicated by the external address signal /ADSP. The pipelining logic 62 comprises a NOR gate having one input tied to the microprocessor produced address and data strobe /ADSP and one input coupled to the module enable signal at third chip enable input 54. In this manner, when the module enable signal at input 54 is at a selected asserted logic level, such as asserted HIGH, pipelining logic 62 blocks the external address signal /ADSP from affecting operation of the SRAM device to thereby permit pipelining operation.
Chip enable and select logic 56. enable register 58, and pipelining logic 62 thereby provide device control circuitry for performing three desired functions: (1 ) selectively enabling or disabling the SRAM device, (2) , selectively permitting access to the SRAM core when the SRAM device is enabled, and (3) selectively permitting pipelining operation of the SRAM device. The circuitry arrangement of this invention achieves these desired features without introducing additional external logic or circuitry. Additionally, this invention accomplishes these desired results through the use of inexpensive logic design comprised of a few logical gates and registers. The invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect.

Claims

WHAT IS CLAIMED IS:
1. A synchronous SRAM module comprising: a first SRAM unit having a memory array and control circuitry for accessing the memory array, the first SRAM unit having first, second, and third chip enable inputs; a second SRAM unit having a memory array and control circuitry for accessing the memory array, the second SRAM unit having first, second, and third chip enable inputs; a module enable and memory selection circuit operably coupled to selectively enable or disable both SRAM units and to choose one of the first and second SRAM units for access, the memory module enable and memory selection circuit generating a module enable signal and a memory select enable signal; the memory select enable signal being coupled to at least one of the first and second chip enable inputs of the first and second SRAM units for selecting the first SRAM unit when the memory select enable signal is at one asserted logic level and for selecting the second SRAM unit when the memory select enable signal is at another asserted logic level; and the module enable signal being coupled to the third chip enable inputs of the first and second SRAM units for enabling operation of both SRAM units when the module enable signal is at one asserted logic level and for disabling operation of both SRAM units when the module enable signal is at another asserted logic level.
2. A synchronous SRAM module according to claim 1 wherein: the memory select enable signal is coupled to the first chip enable input of the first SRAM unit and to the second chip enable input of the second SRAM unit; the second chip enable input of the first SRAM unit is coupled to power; and the first chip enable input of the second SRAM unit is coupled to ground.
3. A synchronous SRAM module according to claim 1 wherein the memory select enable signal is a bit in an address used to access the memory array of one of the first and second SRAM units.
4. A synchronous SRAM device comprising: an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; address control circuitry for accessing a selected location of the memory array within the SRAM core; three chip enable inputs for receiving chip enable signals; and a device control circuit coupled to the SRAM core and the three chip enable inputs, the device control circuit performing the dual tasks of (1 ) selectively enabling or disabling the synchronous SRAM device and (2) selectively permitting access to the SRAM core when enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs.
5. A synchronous SRAM device according to claim 4 wherein the device control circuit comprises: chip enable and select logic coupled to the three chip enable inputs to process the chip enable signals according to the boolean function and output an SRAM core enable signal; and an enable register for temporarily storing the SRAM core enable signal.
6. A synchronous SRAM device according to claim 5 wherein the chip enable and select logic comprises an AND gate having three inputs coupled to the three chip enable inputs and an output coupled to the enable register.
7. A synchronous SRAM device according to claim 4 wherein the chip enable signals comprise /CE, /CE2, and CE2, and the boolean function is defined as:
/CE AND /CE2 AND CE2.
8. A synchronous SRAM device according to claim 4 wherein the address control circuitry includes: an address register for receiving addresses for the memory array in the SRAM core; and a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register.
9. A synchronous SRAM device according to claim 4 further comprising: an input for receiving an external address signal indicating that an external address is waiting at the address control circuit; the device control circuit includes pipelining logic coupled to one of the three chip enable inputs to block the external address signal when the chip enable signal at the one chip enable input is at a selected asserted logic level to thereby permit pipelining operation of the SRAM device.
10. A synchronous burst SRAM device comprising: an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an
SRAM core enable signal resulting from the boolean function of the chip enable signals; an enable register coupled between the chip enable and select logic and the SRAM core for temporarily storing the SRAM core enable signal; and pipelining logic coupled to at least one of the three chip enable inputs to block the external address signal when one chip enable signal received at the one chip enable input is at a selected asserted logic level to thereby permit pipelining operation of the synchronous burst
SRAM device.
11. A synchronous SRAM device according to claim 10 wherein the chip enable and select logic comprises an AND gate having three inputs coupled to the three chip enable inputs and an output coupled to the enable register.
12. A synchronous SRAM device according to claim 10 wherein the chip enable signals comprise /CE, /CE2, and CE2, and the boolean function is defined as:
/CE AND /CE2 AND CE2.
PCT/US1996/002023 1995-02-21 1996-05-10 Synchronous srams having logic for memory expansion WO1996026519A1 (en)

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US5848431A (en) 1998-12-08

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