WO1996039004A3 - Transferring data in a multi-port dram - Google Patents

Transferring data in a multi-port dram Download PDF

Info

Publication number
WO1996039004A3
WO1996039004A3 PCT/US1995/015802 US9515802W WO9639004A3 WO 1996039004 A3 WO1996039004 A3 WO 1996039004A3 US 9515802 W US9515802 W US 9515802W WO 9639004 A3 WO9639004 A3 WO 9639004A3
Authority
WO
WIPO (PCT)
Prior art keywords
dram
atm data
sams
editing
transferring data
Prior art date
Application number
PCT/US1995/015802
Other languages
French (fr)
Other versions
WO1996039004A2 (en
Inventor
Mark R Thomann
Huy Thanh Vo
Glen E Hugh
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP53642696A priority Critical patent/JP3190045B2/en
Publication of WO1996039004A2 publication Critical patent/WO1996039004A2/en
Publication of WO1996039004A3 publication Critical patent/WO1996039004A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/108—ATM switching elements using shared central buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
    • H04L49/405—Physical details, e.g. power supply, mechanical construction or backplane of ATM switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5625—Operations, administration and maintenance [OAM]
    • H04L2012/5627—Fault tolerance and recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Abstract

An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.
PCT/US1995/015802 1995-06-01 1995-12-07 Transferring data in a multi-port dram WO1996039004A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53642696A JP3190045B2 (en) 1995-06-01 1995-12-07 Data transfer in multiport DRAM

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/456,520 1995-06-01
US08/456,520 US5719890A (en) 1995-06-01 1995-06-01 Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM

Publications (2)

Publication Number Publication Date
WO1996039004A2 WO1996039004A2 (en) 1996-12-05
WO1996039004A3 true WO1996039004A3 (en) 1997-02-06

Family

ID=23813088

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/015802 WO1996039004A2 (en) 1995-06-01 1995-12-07 Transferring data in a multi-port dram

Country Status (5)

Country Link
US (3) US5719890A (en)
JP (1) JP3190045B2 (en)
KR (1) KR100264873B1 (en)
TW (1) TW291546B (en)
WO (1) WO1996039004A2 (en)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719890A (en) * 1995-06-01 1998-02-17 Micron Technology, Inc. Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM
US5666390A (en) * 1995-09-28 1997-09-09 Micron Technology, Inc. High speed programmable counter
JPH1064256A (en) * 1996-08-20 1998-03-06 Sony Corp Semiconductor storage
US6487207B1 (en) 1997-02-26 2002-11-26 Micron Technology, Inc. Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology
KR100251735B1 (en) * 1997-12-29 2000-04-15 윤종용 Apparatus and method for preventing common memory loss in atm switch
US6516363B1 (en) 1999-08-06 2003-02-04 Micron Technology, Inc. Output data path having selectable data rates
US6694416B1 (en) 1999-09-02 2004-02-17 Micron Technology, Inc. Double data rate scheme for data output
US6701480B1 (en) 2000-03-08 2004-03-02 Rockwell Automation Technologies, Inc. System and method for providing error check and correction in memory systems
US6792567B2 (en) * 2001-04-30 2004-09-14 Stmicroelectronics, Inc. System and method for correcting soft errors in random access memory devices
US6868487B2 (en) * 2001-10-01 2005-03-15 International Business Machines Corporation Data storage device and method for storing information using alternate information storage architectures
US7571287B2 (en) * 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
US7305608B2 (en) * 2003-09-25 2007-12-04 Broadcom Corporation DSL trellis encoding
US20050094551A1 (en) * 2003-09-25 2005-05-05 Broadcom Corporation Processor instruction for DMT encoding
US7903810B2 (en) 2003-09-26 2011-03-08 Broadcom Corporation Single instruction for data scrambling
US7751557B2 (en) * 2003-09-26 2010-07-06 Broadcom Corporation Data de-scrambler
US7734041B2 (en) * 2003-09-26 2010-06-08 Broadcom Corporation System and method for de-scrambling and bit-order-reversing payload bytes in an Asynchronous Transfer Mode cell
US7580412B2 (en) * 2003-09-26 2009-08-25 Broadcom Corporation System and method for generating header error control byte for Asynchronous Transfer Mode cell
US7756273B2 (en) * 2003-09-26 2010-07-13 Broadcom Corporation System and method for bit-reversing and scrambling payload bytes in an asynchronous transfer mode cell
US7630382B1 (en) * 2003-10-16 2009-12-08 Network Equipment Technologies, Inc. Method and system for providing transport of channelized circuits of arbitrary bit rate through asynchronous transfer mode (ATM) circuit emulation services (CES)
US7747933B2 (en) * 2005-07-21 2010-06-29 Micron Technology, Inc. Method and apparatus for detecting communication errors on a bus
GB0519595D0 (en) * 2005-09-26 2005-11-02 Barnes Charles F J Improvements in data storage and manipulation
US8234425B1 (en) 2007-06-27 2012-07-31 Marvell International Ltd. Arbiter module
US7949817B1 (en) 2007-07-31 2011-05-24 Marvell International Ltd. Adaptive bus profiler
US8131915B1 (en) 2008-04-11 2012-03-06 Marvell Intentional Ltd. Modifying or overwriting data stored in flash memory
US8683085B1 (en) 2008-05-06 2014-03-25 Marvell International Ltd. USB interface configurable for host or device mode
US8423710B1 (en) 2009-03-23 2013-04-16 Marvell International Ltd. Sequential writes to flash memory
US8213236B1 (en) 2009-04-21 2012-07-03 Marvell International Ltd. Flash memory
US8239745B2 (en) * 2009-06-02 2012-08-07 Freescale Semiconductor, Inc. Parity data encoder for serial communication
US8688922B1 (en) 2010-03-11 2014-04-01 Marvell International Ltd Hardware-supported memory management
US8756394B1 (en) 2010-07-07 2014-06-17 Marvell International Ltd. Multi-dimension memory timing tuner
CN104579548B (en) * 2013-10-29 2019-09-10 南京中兴新软件有限责任公司 Transmission method and device based on management data input and output multi-source agreement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01181142A (en) * 1988-01-14 1989-07-19 Fujitsu Ltd Parity control system for dual port memory
US5394399A (en) * 1990-08-10 1995-02-28 Fujitsu Limited Communication control system
WO1995014269A1 (en) * 1993-11-19 1995-05-26 The Trustees Of The University Of Pennsylvania A high-performance host interface for networks carrying connectionless traffic

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4070710A (en) * 1976-01-19 1978-01-24 Nugraphics, Inc. Raster scan display apparatus for dynamically viewing image elements stored in a random access memory array
GB1568379A (en) * 1976-02-19 1980-05-29 Micro Consultants Ltd Video store
US4120048A (en) * 1977-12-27 1978-10-10 Rockwell International Corporation Memory with simultaneous sequential and random address modes
JPS56145300A (en) * 1980-04-14 1981-11-11 Takeda Chem Ind Ltd N2-pyridyl-2,6-diaminonebularine
HU180133B (en) * 1980-05-07 1983-02-28 Szamitastech Koord Equipment for displaying and storing tv picture information by means of useiof a computer access memory
JPS57186289A (en) * 1981-05-13 1982-11-16 Hitachi Ltd Semiconductor memory
JPS57198592A (en) * 1981-05-29 1982-12-06 Hitachi Ltd Semiconductor memory device
US4513392A (en) * 1982-05-25 1985-04-23 Honeywell Information Systems Inc. Method and apparatus for generating a repetitive serial pattern using a recirculating shift register
US4891749A (en) * 1983-03-28 1990-01-02 International Business Machines Corporation Multiprocessor storage serialization apparatus
US4646270A (en) * 1983-09-15 1987-02-24 Motorola, Inc. Video graphic dynamic RAM
US4747081A (en) * 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
JPS60205895A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Semiconductor memory
JPS6159688A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Semiconductor integrated circuit device
US4648077A (en) * 1985-01-22 1987-03-03 Texas Instruments Incorporated Video serial accessed memory with midline load
US5093787A (en) * 1986-06-12 1992-03-03 Simmons John C Electronic checkbook with automatic reconciliation
US5249159A (en) * 1987-05-27 1993-09-28 Hitachi, Ltd. Semiconductor memory
JP2615088B2 (en) * 1987-11-06 1997-05-28 株式会社日立製作所 Semiconductor storage device
JPH07107792B2 (en) * 1988-01-19 1995-11-15 株式会社東芝 Multiport memory
JPH01200455A (en) * 1988-02-05 1989-08-11 Sharp Corp Parity function test method for semiconductor memory having parity function
US4891794A (en) * 1988-06-20 1990-01-02 Micron Technology, Inc. Three port random access memory
US5058051A (en) * 1988-07-29 1991-10-15 Texas Medical Instruments, Inc. Address register processor system
EP0363053B1 (en) * 1988-10-06 1998-01-14 Gpt Limited Asynchronous time division switching arrangement and a method of operating same
US5001671A (en) * 1989-06-27 1991-03-19 Vitelic Corporation Controller for dual ported memory
US5204841A (en) * 1990-07-27 1993-04-20 International Business Machines Corporation Virtual multi-port RAM
US5187785A (en) * 1990-12-28 1993-02-16 General Electric Company Algorithm for representing component connectivity
US5392302A (en) * 1991-03-13 1995-02-21 Quantum Corp. Address error detection technique for increasing the reliability of a storage subsystem
EP0505926B1 (en) * 1991-03-19 1997-01-02 Fujitsu Limited Multiport memory
JPH0612863A (en) * 1992-06-26 1994-01-21 Toshiba Corp Dual port dram
JP2667941B2 (en) * 1992-09-17 1997-10-27 三菱電機株式会社 Memory cell circuit
US5506814A (en) * 1993-05-28 1996-04-09 Micron Technology, Inc. Video random access memory device and method implementing independent two WE nibble control
JP2768621B2 (en) * 1993-06-25 1998-06-25 沖電気工業株式会社 Decoding apparatus for convolutional code transmitted in a distributed manner
US5732041A (en) * 1993-08-19 1998-03-24 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
US5617367A (en) * 1993-09-01 1997-04-01 Micron Technology, Inc. Controlling synchronous serial access to a multiport memory
US5452259A (en) * 1993-11-15 1995-09-19 Micron Technology Inc. Multiport memory with pipelined serial input
US5488584A (en) * 1994-08-26 1996-01-30 Micron Technology, Inc. Circuit and method for externally controlling signal development in a serial access memory
US5719890A (en) * 1995-06-01 1998-02-17 Micron Technology, Inc. Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM
US5592488A (en) * 1995-06-07 1997-01-07 Micron Technology, Inc. Method and apparatus for pipelined multiplexing employing analog delays for a multiport interface
US5680595A (en) * 1995-06-07 1997-10-21 Micron Technology, Inc. Programmable data port clocking system for clocking a plurality of data ports with a plurality of clocking signals in an asynchronous transfer mode system
US5657289A (en) * 1995-08-30 1997-08-12 Micron Technology, Inc. Expandable data width SAM for a multiport RAM
US5666390A (en) * 1995-09-28 1997-09-09 Micron Technology, Inc. High speed programmable counter
US5680425A (en) * 1995-09-28 1997-10-21 Micron Technology, Inc. Self-queuing serial output port
US5815447A (en) * 1996-08-08 1998-09-29 Micron Technology, Inc. Memory device having complete row redundancy

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01181142A (en) * 1988-01-14 1989-07-19 Fujitsu Ltd Parity control system for dual port memory
US5394399A (en) * 1990-08-10 1995-02-28 Fujitsu Limited Communication control system
WO1995014269A1 (en) * 1993-11-19 1995-05-26 The Trustees Of The University Of Pennsylvania A high-performance host interface for networks carrying connectionless traffic

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, (P - 947) 20 October 1989 (1989-10-20) *

Also Published As

Publication number Publication date
KR100264873B1 (en) 2000-09-01
WO1996039004A2 (en) 1996-12-05
JP3190045B2 (en) 2001-07-16
US6081528A (en) 2000-06-27
KR19990021889A (en) 1999-03-25
US5778007A (en) 1998-07-07
JPH10506776A (en) 1998-06-30
US5719890A (en) 1998-02-17
TW291546B (en) 1996-11-21

Similar Documents

Publication Publication Date Title
WO1996039004A3 (en) Transferring data in a multi-port dram
MY105290A (en) Dynamic ram with on-chip ecc and optimized bit and word redundancy.
TW345660B (en) Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell
TW324823B (en) Cross-coupled bitline segments for generalized data propagation
EP0346629A3 (en) Memory card architecture and interface
TW274138B (en) Expandable data width sam for a multiport ram
EP0206784A3 (en) Dual array memory
TW331007B (en) Semiconductor memory device
EP0304286A3 (en) Semiconductor integrated circuit device having logic macro and random access memory macro
EP0778575A3 (en) Dynamic random access memory
MY108976A (en) Multiport memory with test signal generating circuit controlling data transfer from ram port to sam port
EP1150211A3 (en) Redundant memory cell for dynamic random access memories having twisted bit line architectures
EP0166309A3 (en) Memory chip for a hierarchical memory system
EP0326172A3 (en) Memory circuit with improved serial access circuit arrangement
HK106193A (en) Method and circuit arrangement for the parallel write-in of data in a semiconductor memory
US5117395A (en) Expansible FIFO memory for accommodating added memory stages in a multistage memory with common control signals
CA2026741A1 (en) Main storage memory cards having single bit set and reset functions
TW332355B (en) Semiconductor device having a latch circuit for latching externally input data
Endo et al. Pipelined, time-sharing access technique for an integrated multiport memory
US3836892A (en) D.c. stable electronic storage utilizing a.c. stable storage cell
TW344072B (en) Redundant recovery circuit
EP0788107A3 (en) Semiconductor memory device
EP0214050B1 (en) Parallel row-to-row data transfer in random access memories
EP0153015A3 (en) Wafer scale integrated circuits
US6611929B1 (en) Test circuit for memory

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1019970708364

Country of ref document: KR

122 Ep: pct application non-entry in european phase
WWP Wipo information: published in national office

Ref document number: 1019970708364

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1019970708364

Country of ref document: KR