WO1998013763A2 - Multiport cache memory with address conflict detection - Google Patents
Multiport cache memory with address conflict detection Download PDFInfo
- Publication number
- WO1998013763A2 WO1998013763A2 PCT/IB1997/001146 IB9701146W WO9813763A2 WO 1998013763 A2 WO1998013763 A2 WO 1998013763A2 IB 9701146 W IB9701146 W IB 9701146W WO 9813763 A2 WO9813763 A2 WO 9813763A2
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- port
- bank
- cache
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0851—Cache with interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
Definitions
- the present invention relates to a processing system with a cache memory, and more particularly to a cache having multiple access ports.
- a cache is a small, fast memory placed between a processor and main memory in order to reduce the effective time required by a processor to access addresses, instructions or data that are normally stored in main memory. For example, when a processor reads a word from main memory, the word and neighbouring words are read as a block from main memory into the cache. Typically, there is a high probability that the processor will next attempt to access one of the neighbouring words within the block. Because of this locality of reference property, main memory bus traffic is reduced since the processor is likely to engage in subsequent data transactions directly with the cache. Cache accesses take less time than main memory accesses. Consequently, the use of a cache increases processor throughput.
- the processor may attempt to execute memory operations simultaneously. In those cases, the processor may require simultaneous access to multiple words stored within cache memory. Accordingly, the cache may include multiple ports, each port for conducting a separate data transaction.
- a multi-port cache may be implemented as a single multi-port SRAM. However, such a configuration is very slow in operation and occupies a relatively large chip area.
- a dual-port cache may be implemented with two single-port memory arrays, each corresponding to one of the cache ports. The two arrays have the same address space. This cumbersome arrangement requires complex data coherency circuitry to ensure that the arrays store the same data when data is modified at one of the cache ports. Further, the use of two arrays to store redundant copies of the same data occupies an unnecessarily large chip area.
- the present invention provides a multi-port cache memory.
- the multi- port cache operates in a microprocessor system, and includes multiple memory banks and multiple ports for enabling accesses to the banks.
- Conflict detection circuitry detects simultaneous addressing of a first memory bank through a first port and a second port, and stalls microprocessor operations for a predetermined number of clock cycles in response to the detection of simultaneous addressing.
- Conflict resolution circuitry allows access to the first bank through the first port during the stall, and allows access through the second port after the stall is complete.
- the conflict resolution circuitry allows access through ports that are attempting to access the first memory bank in order of ascending priority during successive clock cycles while the microprocessor is stalled.
- One or more of the ports attempting to access the first bank may be allowed access before or after the time the microprocessor is stalled.
- Each bank is single-ported. The banks have non overlapping address spaces, and are addressed so that words within a cache block are distributed among multiple banks.
- Figure 1 illustrates a computer system having a multi-port cache of the present invention.
- Figure 2 is a block diagram illustrating a processor coupled to a multi- port cache of the present invention.
- Figure 3A is a timing diagram illustrating cache timing in the absence of a bank conflict.
- Figure 3B is a timing diagram illustrating cache timing in the presence of a bank conflict.
- FIG. 1 illustrates a computer system having a multi-port CPU 100, a main memory 102, a main memory interface 104, and a multi-port cache 106 of the present invention.
- the main memory interface 104 manages the information exchange between the cache 106 and main memory 102 to maintain cache coherency when a CPU access misses the cache or when the CPU writes new data into the cache.
- the cache 106 is shown as having two ports, although those skilled in the art will recognize that the present invention is easily extended to a cache having any number of ports.
- the processor is capable of executing multiple parallel operations, and thus may require simultaneous access to more than one word stored within the cache.
- processors or other agents may each require access to a corresponding cache port.
- FIG. 2 is a detailed block diagram of a processor 100 coupled to an embodiment of the cache 106 of the present invention.
- the cache is a two- way set-associative cache.
- the cache of the present invention does not employ a dual-port SRAM or redundant single-port arrays that store the same data.
- the present invention employs multiple single-port memory banks, where each bank stores data for a non-overlapping address space.
- each bank may be accessed by any of the ports. As long as no two ports attempt to access the same bank, all ports can execute simultaneous accesses to the cache.
- the cache controls the timing of the accesses as described below.
- the CPU 100 can issue multiple accesses to the cache 106, represented as a first address A0 and a second address Al. These addresses correspond to the two ports 201 and 203 of the cache of this example.
- the cache itself comprises a first bank 200, bankO, and a second bank 202, bankl.
- each bank holds eight kilobytes (8 KB) of data, where four bytes comprise one 32-bit word.
- each bank stores 2K words.
- each cache block is two words long, and two blocks comprise one set of the two-way set-associative cache of this example.
- Each bank is coupled to a plurality of read buses 204 through a corresponding tri-state bus driver 206, each read bus 204 corresponding to one of the ports.
- Each bank is further coupled to a plurality of write buses 208 through a write multiplexer 210, each write bus 208 corresponding to one of the ports.
- the read and write busses 204, 208 are coupled to the input/output ports of the CPU 100 (the coupling is not shown to keep the figure simple).
- each port is coupled to a dual tag RAM 212, where each tag array 214 corresponds to a way of the two-way set-associative cache.
- the tag from each array is fed into a corresponding comparator, 216 which compares the tag to the tag field of the corresponding port address.
- the resulting hit signal is passed to a corresponding port input of a hit multiplexer 218 for each bank.
- the hit signal here is a two-bit "one hot" signal in which at most one bit may take on a logical one value.
- Each bank also is coupled to a row multiplexer 220 that receives the set index field of each port address.
- read/write control signals are passed from each CPU port to a corresponding input of a read/write multiplexer (not shown) for each bank to indicate whether a read or write memory operation is to be performed.
- a write enable signal from each port is passed to a corresponding input of a write multiplexer.
- a read enable signal from each port is passed to a corresponding input of a read multiplexer.
- the output of the multiplexers is coupled to write enable and read enable inputs, respectively, of the corresponding bank.
- the read and write multiplexers together are referred to herein as the "read/write multiplexer.”
- the address circuitry that is common to both ports includes conflict detect circuitry 222 that receives the bank address portion of the port addresses.
- each bank address passes through a 1:2 bank decoder 224, which produces a bank select signal in response. For example, if a zero bank address bit represents a selection of bankO, then the bank decoder 224 will output a one from its bankO output and a zero from its bankl output.
- the bank select signal (bd) from each port's decoder is fed into a corresponding conflict resolution circuit 226 for each bank.
- the output of the conflict resolution circuitry 226 controls the row multiplexer 220, the hit multiplexer 218 and the read/ write multiplexer (not shown) for each bank to determine which port will have access to the bank.
- the conflict resolution circuitry 226 also controls the tri-state drivers 206 for the read buses 204 ( Figure 2 assumes active high) and the write bus multiplexers 210 to assure access to the bus corresponding to the selected port.
- each bank stores 8 KB of data with each word comprising four bytes.
- Each cache block comprises two words.
- the memory contains IK sets with two blocks per set because the cache is a two-way set-associative cache. Bit 2 of the address selects the bank, whereas bits 3-12 select one of the sets. Bits 13-31 of the address are used in the tag comparison to indicate the presence of an addressed block in the cache.
- Figure 3A illustrates cache timing where there is no bank conflict.
- Figure 3B illustrates cache timing with a bank conflict.
- the CPU attempts to perform simultaneous accesses of the cache by issuing an address AO from a first CPU port 228 and an address Al from a second CPU port 230.
- the addresses are respectively received by a first cache port 201 and a second cache port 203 over an internal CPU bus 232.
- the second bits of the addresses are fed into the conflict detection circuitry 222 to determine whether both ports are attempting to access the same memory bank.
- the conflict resolution circuitry 226 determines which port input will be passed by the row multiplexer 220, the hit multiplexer 218 and the read/write multiplexer to each bank, and selects the proper read or write bus to communicate with the bank (depending upon whether a read or write operation is being performed) .
- the two-bit signal selO represents the two port- select signals for bankO
- the two-bit signal sell represents the two port-select signals for bankl. These combined signals select the appropriate port input to the multiplexers.
- the conflict resolution logic may be implemented by any circuitry that embodies the logic of Table 1.
- x/y indicates that the port select signal takes on a value of x in one clock cycle followed by a value of y in a subsequent clock cycle.
- the conflict resolution circuitry 226 determines which port communicates with each bank. This selection is based upon the bank address field of the port addresses, which is bit 2 in this example. The other bits are used to address a particular word within the banks. Bits 3-12 are the set index fed into the dual tag array for each port. In this example, a set comprises two blocks, with one block in each bank. Bits 13-31 comprise the tag address field that is compared to the tags from the dual tag array 212.
- the hit signal selects the word within the block.
- the miss is handled by loading the miss block into the cache. Operation resumes as if the miss did not occur, resulting in a hit. For example, if one instruction attempts two simultaneous accesses and one port hits while the other port misses, the miss is first handled. Then, the instruction is restarted, resulting in two hits with the conflict resolution circuitry operating as described herein.
- the set index and the hit signal are routed to the correct bank through the multiplexers controlled by the conflict resolution circuitry 226. Assume hits for both port addresses.
- the hit signal, hitO, from portO 201 is routed through the hit multiplexers 218 to the hit input of bankO 220, whereas the hit signal, hitl, from portl 203 is routed through the hit multiplexers 218 to the hit input of bankl 202.
- the data read from or written to portO 201 is represented by X
- the data read from or written to portl 203 is represented by Y.
- both of these ports are in communication with a bank.
- X data from portO 201 is read from or written to bankO 200
- Y data from portl 203 is read from or written to bankl 202.
- Figure 3B is a timing diagram illustrating the operation of the cache of the present invention in case of a bank conflict.
- the conflict detection circuitry 222 will stall the operations of the CPU 100 in the next cycle, i.e., cycle 1.
- the mechanism employed by the conflict detection circuitry 222 to stall the CPU can be implemented using circuitry similar to that employed by standard cache control logic to stall the CPU during a cache miss.
- the bank select signals for each bank are OR'ed together by an OR gate 250 having an output fed into a bank enable input. If no port attempts to access a bank, then the bank is not enabled. Here, bankl is not being accessed.
- sel_ctrl is asserted during the stall (cycle 1) so as to force selO to select portl during cycle 1. See Figure 3B and Table 1.
- the hit signal, hitl, from portl is routed through the hit multiplexers 218 to the hit_bank0 input, of bankO so that the data word Y can be outputted through portl during the next cycle, cycle 2.
- the result of a read operation for portO is latched on the read bus for portO by latching circuitry on the bus (not shown).
- data X read from portO and data Y from portl appear simultaneously during cycle 2. Because CPU operations are stalled during cycle 1 , it appears to the CPU that the dual port cache access occurs simultaneously in a cycle immediately following cycle 0.
- conflict resolution circuitry 226 grants priority access to portO in case of a conflict.
- the conflict resolution circuitry 226 may grant access to conflicting ports in any order of priority.
- the ports are numbered so that low-numbered ports correspond to those requiring high-priority access, whereas high-numbered ports can wait longer for access.
- sel_ctrll There are two selection control signals, shared by all banks, to override priorities of bank conflict resolution: sel_ctrll, sel_ctrl2. If sel_ctrll is asserted, then port 1 is selected. If sel_ctrl2 is asserted, then port 2 is selected. If neither sel_ctrll nor sel_ctrl2 is asserted, then port 0 has priority.
- bank conflicts are avoided in the compiler and application software by allocating variables in nearby instructions to addresses in different banks. Thus, it is highly unlikely that the same bank would be addressed in the same cycle. Further, the organization of the address space itself helps to reduce the chance of a bank conflict. By using lower order address bits, e.g., the second bit, to select the bank, adjacent words of the cache block are evenly distributed among all the banks. In this manner, the addressing of adjacent words will result in the addressing of different banks. Because of the locality of reference property, this organization thus reduces the chance of conflict.
- the cache can be organized as an eight-way set-associative cache of eight banks.
- address bits 6-10 act as the set index.
- Each set comprises two rows in each bank.
- Bit 5 selects one of the two rows, and bits 2-4 select the bank.
- the address bits 11-31 are used for the tag comparison.
- Bits 0-1 correspond to the byte within a word.
- the present invention can be applied to a pipelined cache.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10515453A JP2000501539A (en) | 1996-09-25 | 1997-09-23 | Multi-port cache memory with address conflict detection |
KR1019980703828A KR19990071554A (en) | 1996-09-25 | 1997-09-23 | Multi-port cache memory with address conflict detection |
EP97940270A EP0875030A2 (en) | 1996-09-25 | 1997-09-23 | Multi-port cache memory with address conflict detection |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US71960996A | 1996-09-25 | 1996-09-25 | |
US08/719,609 | 1996-09-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998013763A2 true WO1998013763A2 (en) | 1998-04-02 |
WO1998013763A3 WO1998013763A3 (en) | 1998-06-04 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1997/001146 WO1998013763A2 (en) | 1996-09-25 | 1997-09-23 | Multiport cache memory with address conflict detection |
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---|---|
EP (1) | EP0875030A2 (en) |
JP (1) | JP2000501539A (en) |
KR (1) | KR19990071554A (en) |
WO (1) | WO1998013763A2 (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999045474A2 (en) * | 1998-03-06 | 1999-09-10 | Pact Informationstechnologie Gmbh | Speed-optimized cache system |
WO2001074134A2 (en) * | 2000-03-31 | 2001-10-11 | Intel Corporation | System having a configurable cache/sram memory |
US6539457B1 (en) * | 2000-02-21 | 2003-03-25 | Hewlett-Packard Company | Cache address conflict mechanism without store buffers |
US6557078B1 (en) * | 2000-02-21 | 2003-04-29 | Hewlett Packard Development Company, L.P. | Cache chain structure to implement high bandwidth low latency cache memory subsystem |
US6606684B1 (en) | 2000-03-31 | 2003-08-12 | Intel Corporation | Multi-tiered memory bank having different data buffer sizes with a programmable bank select |
WO2004049171A2 (en) * | 2002-11-26 | 2004-06-10 | Advanced Micro Devices, Inc. | Microprocessor including cache memory supporting multiple accesses per cycle |
WO2007111492A1 (en) * | 2006-03-29 | 2007-10-04 | Fidelix Co., Ltd. | Multi-port memory device including plurality of shared blocks |
US7769950B2 (en) | 2004-03-24 | 2010-08-03 | Qualcomm Incorporated | Cached memory system and cache controller for embedded digital signal processor |
CN102622192A (en) * | 2012-02-27 | 2012-08-01 | 北京理工大学 | Weak correlation multiport parallel store controller |
US8583873B2 (en) | 2010-03-10 | 2013-11-12 | Samsung Electronics Co., Ltd. | Multiport data cache apparatus and method of controlling the same |
US8977800B2 (en) | 2011-02-25 | 2015-03-10 | Samsung Electronics Co., Ltd. | Multi-port cache memory apparatus and method |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100780621B1 (en) * | 2005-09-29 | 2007-11-29 | 주식회사 하이닉스반도체 | Multi port memory device |
US7613065B2 (en) | 2005-09-29 | 2009-11-03 | Hynix Semiconductor, Inc. | Multi-port memory device |
US9171594B2 (en) * | 2012-07-19 | 2015-10-27 | Arm Limited | Handling collisions between accesses in multiport memories |
KR102346629B1 (en) * | 2014-12-05 | 2022-01-03 | 삼성전자주식회사 | Method and apparatus for controlling access for memory |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5056002A (en) * | 1987-02-09 | 1991-10-08 | Nec Corporation | Cache memory for use with multiprocessor systems |
US5274790A (en) * | 1990-04-30 | 1993-12-28 | Nec Corporation | Cache memory apparatus having a plurality of accessibility ports |
US5276850A (en) * | 1988-12-27 | 1994-01-04 | Kabushiki Kaisha Toshiba | Information processing apparatus with cache memory and a processor which generates a data block address and a plurality of data subblock addresses simultaneously |
US5434989A (en) * | 1991-02-19 | 1995-07-18 | Matsushita Electric Industrial Co., Ltd. | Cache memory for efficient access with address selectors |
-
1997
- 1997-09-23 WO PCT/IB1997/001146 patent/WO1998013763A2/en not_active Application Discontinuation
- 1997-09-23 EP EP97940270A patent/EP0875030A2/en not_active Withdrawn
- 1997-09-23 KR KR1019980703828A patent/KR19990071554A/en not_active Application Discontinuation
- 1997-09-23 JP JP10515453A patent/JP2000501539A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5056002A (en) * | 1987-02-09 | 1991-10-08 | Nec Corporation | Cache memory for use with multiprocessor systems |
US5276850A (en) * | 1988-12-27 | 1994-01-04 | Kabushiki Kaisha Toshiba | Information processing apparatus with cache memory and a processor which generates a data block address and a plurality of data subblock addresses simultaneously |
US5274790A (en) * | 1990-04-30 | 1993-12-28 | Nec Corporation | Cache memory apparatus having a plurality of accessibility ports |
US5434989A (en) * | 1991-02-19 | 1995-07-18 | Matsushita Electric Industrial Co., Ltd. | Cache memory for efficient access with address selectors |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999045474A3 (en) * | 1998-03-06 | 1999-11-11 | Pact Inf Tech Gmbh | Speed-optimized cache system |
WO1999045474A2 (en) * | 1998-03-06 | 1999-09-10 | Pact Informationstechnologie Gmbh | Speed-optimized cache system |
US6539457B1 (en) * | 2000-02-21 | 2003-03-25 | Hewlett-Packard Company | Cache address conflict mechanism without store buffers |
US6557078B1 (en) * | 2000-02-21 | 2003-04-29 | Hewlett Packard Development Company, L.P. | Cache chain structure to implement high bandwidth low latency cache memory subsystem |
US6898690B2 (en) | 2000-03-31 | 2005-05-24 | Intel Corporation | Multi-tiered memory bank having different data buffer sizes with a programmable bank select |
WO2001074134A2 (en) * | 2000-03-31 | 2001-10-11 | Intel Corporation | System having a configurable cache/sram memory |
WO2001074134A3 (en) * | 2000-03-31 | 2002-05-23 | Intel Corp | System having a configurable cache/sram memory |
US6606684B1 (en) | 2000-03-31 | 2003-08-12 | Intel Corporation | Multi-tiered memory bank having different data buffer sizes with a programmable bank select |
EP2312447A1 (en) * | 2000-03-31 | 2011-04-20 | Intel Corporation | System having a configurable cache/SRAM memory |
US6446181B1 (en) | 2000-03-31 | 2002-09-03 | Intel Corporation | System having a configurable cache/SRAM memory |
US7073026B2 (en) | 2002-11-26 | 2006-07-04 | Advanced Micro Devices, Inc. | Microprocessor including cache memory supporting multiple accesses per cycle |
WO2004049171A3 (en) * | 2002-11-26 | 2004-11-04 | Advanced Micro Devices Inc | Microprocessor including cache memory supporting multiple accesses per cycle |
CN1717664B (en) * | 2002-11-26 | 2010-10-27 | 先进微装置公司 | Microprocessor, cache memory sub-system and cumputer system |
WO2004049171A2 (en) * | 2002-11-26 | 2004-06-10 | Advanced Micro Devices, Inc. | Microprocessor including cache memory supporting multiple accesses per cycle |
US7769950B2 (en) | 2004-03-24 | 2010-08-03 | Qualcomm Incorporated | Cached memory system and cache controller for embedded digital signal processor |
US8316185B2 (en) | 2004-03-24 | 2012-11-20 | Qualcomm Incorporated | Cached memory system and cache controller for embedded digital signal processor |
WO2007111492A1 (en) * | 2006-03-29 | 2007-10-04 | Fidelix Co., Ltd. | Multi-port memory device including plurality of shared blocks |
US8583873B2 (en) | 2010-03-10 | 2013-11-12 | Samsung Electronics Co., Ltd. | Multiport data cache apparatus and method of controlling the same |
US8977800B2 (en) | 2011-02-25 | 2015-03-10 | Samsung Electronics Co., Ltd. | Multi-port cache memory apparatus and method |
CN102622192A (en) * | 2012-02-27 | 2012-08-01 | 北京理工大学 | Weak correlation multiport parallel store controller |
Also Published As
Publication number | Publication date |
---|---|
EP0875030A2 (en) | 1998-11-04 |
JP2000501539A (en) | 2000-02-08 |
WO1998013763A3 (en) | 1998-06-04 |
KR19990071554A (en) | 1999-09-27 |
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