WO2005033959A1 - Memory buffer device integrating refresh - Google Patents
Memory buffer device integrating refresh Download PDFInfo
- Publication number
- WO2005033959A1 WO2005033959A1 PCT/US2004/032039 US2004032039W WO2005033959A1 WO 2005033959 A1 WO2005033959 A1 WO 2005033959A1 US 2004032039 W US2004032039 W US 2004032039W WO 2005033959 A1 WO2005033959 A1 WO 2005033959A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- storage array
- refresh
- interface
- memory controller
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Memory System (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04785279A EP1668524A1 (en) | 2003-09-29 | 2004-09-29 | Memory buffer device integrating refresh |
JP2006528329A JP2007507056A (en) | 2003-09-29 | 2004-09-29 | Memory device, interface buffer, memory system, computer system, method, machine accessible medium |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/674,981 | 2003-09-29 | ||
US10/674,981 US7353329B2 (en) | 2003-09-29 | 2003-09-29 | Memory buffer device integrating refresh logic |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005033959A1 true WO2005033959A1 (en) | 2005-04-14 |
Family
ID=34377006
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/032039 WO2005033959A1 (en) | 2003-09-29 | 2004-09-29 | Memory buffer device integrating refresh |
Country Status (6)
Country | Link |
---|---|
US (1) | US7353329B2 (en) |
EP (1) | EP1668524A1 (en) |
JP (1) | JP2007507056A (en) |
CN (1) | CN100472492C (en) |
TW (1) | TWI252487B (en) |
WO (1) | WO2005033959A1 (en) |
Families Citing this family (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7328304B2 (en) * | 2004-02-27 | 2008-02-05 | Intel Corporation | Interface for a block addressable mass storage system |
US7609567B2 (en) * | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US7580312B2 (en) * | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
GB2441726B (en) * | 2005-06-24 | 2010-08-11 | Metaram Inc | An integrated memory core and memory interface circuit |
US7472220B2 (en) * | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US20080082763A1 (en) * | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US7392338B2 (en) * | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
DE112006004263B4 (en) * | 2005-09-02 | 2015-05-13 | Google, Inc. | memory chip |
US9632929B2 (en) * | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US20080028135A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Multiple-component memory interface system and method |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
JP4198167B2 (en) * | 2006-09-20 | 2008-12-17 | 株式会社ソニー・コンピュータエンタテインメント | Adapter device, data transmission system |
US8239637B2 (en) * | 2007-01-19 | 2012-08-07 | Spansion Llc | Byte mask command for memories |
JP4561783B2 (en) * | 2007-06-21 | 2010-10-13 | ソニー株式会社 | Semiconductor memory device and method of operating semiconductor memory device |
JP4561782B2 (en) * | 2007-06-21 | 2010-10-13 | ソニー株式会社 | Semiconductor memory device and method of operating semiconductor memory device |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
JP2010237739A (en) * | 2009-03-30 | 2010-10-21 | Fujitsu Ltd | Cache controlling apparatus, information processing apparatus, and cache controlling program |
WO2010123681A2 (en) | 2009-04-22 | 2010-10-28 | Rambus Inc. | Protocol for refresh between a memory controller and a memory device |
EP2441007A1 (en) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programming of dimm termination resistance values |
US8392650B2 (en) * | 2010-04-01 | 2013-03-05 | Intel Corporation | Fast exit from self-refresh state of a memory device |
US8751802B2 (en) | 2010-06-30 | 2014-06-10 | Sandisk Il Ltd. | Storage device and method and for storage device state recovery |
US9053812B2 (en) * | 2010-09-24 | 2015-06-09 | Intel Corporation | Fast exit from DRAM self-refresh |
US9292426B2 (en) * | 2010-09-24 | 2016-03-22 | Intel Corporation | Fast exit from DRAM self-refresh |
KR101796116B1 (en) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | Semiconductor device, memory module and memory system having the same and operating method thereof |
CN102034526B (en) * | 2010-12-17 | 2013-06-12 | 曙光信息产业股份有限公司 | Method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA) |
US9159396B2 (en) * | 2011-06-30 | 2015-10-13 | Lattice Semiconductor Corporation | Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices |
US20130042132A1 (en) * | 2011-08-09 | 2013-02-14 | Samsung Electronics Co., Ltd. | Image forming appratus, microcontroller, and methods for controlling image forming apparatus and microcontroller |
US9104420B2 (en) | 2011-08-09 | 2015-08-11 | Samsung Electronics Co., Ltd. | Image forming apparatus, microcontroller, and methods for controlling image forming apparatus and microcontroller |
CN102567243B (en) * | 2011-12-12 | 2015-03-25 | 华为技术有限公司 | Storage device and refreshing method for same |
CN102426854A (en) * | 2011-12-13 | 2012-04-25 | 曙光信息产业(北京)有限公司 | Method for lowering DDR3 (Double Data Rate) memory refreshing power consumption |
US9299400B2 (en) | 2012-09-28 | 2016-03-29 | Intel Corporation | Distributed row hammer tracking |
US9087614B2 (en) | 2012-11-27 | 2015-07-21 | Samsung Electronics Co., Ltd. | Memory modules and memory systems |
US9286964B2 (en) * | 2012-12-21 | 2016-03-15 | Intel Corporation | Method, apparatus and system for responding to a row hammer event |
US9153310B2 (en) | 2013-01-16 | 2015-10-06 | Maxlinear, Inc. | Dynamic random access memory for communications systems |
US9911485B2 (en) * | 2013-11-11 | 2018-03-06 | Qualcomm Incorporated | Method and apparatus for refreshing a memory cell |
US9087569B2 (en) * | 2013-11-26 | 2015-07-21 | Lenovo (Singapore) Pte. Ltd. | Non-volatile memory validity |
FR3032814B1 (en) * | 2015-02-18 | 2018-02-02 | Upmem | DRAM CIRCUIT WITH INTEGRATED PROCESSOR |
US20170110178A1 (en) * | 2015-09-17 | 2017-04-20 | Intel Corporation | Hybrid refresh with hidden refreshes and external refreshes |
US20170163312A1 (en) * | 2015-12-03 | 2017-06-08 | Samsung Electronics Co., Ltd. | Electronic system with network operation mechanism and method of operation thereof |
JP2018041154A (en) * | 2016-09-05 | 2018-03-15 | 東芝メモリ株式会社 | Storage system and processing method |
US10825534B2 (en) | 2018-10-26 | 2020-11-03 | Intel Corporation | Per row activation count values embedded in storage cell array storage cells |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5689677A (en) * | 1995-06-05 | 1997-11-18 | Macmillan; David C. | Circuit for enhancing performance of a computer for personal use |
US5859809A (en) * | 1996-12-31 | 1999-01-12 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device of daisy chain structure having independent refresh apparatus |
WO1999030240A1 (en) * | 1997-12-05 | 1999-06-17 | Intel Corporation | Memory system including a memory module having a memory module controller |
US20010008496A1 (en) * | 1999-01-20 | 2001-07-19 | Wingyu Leung | Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory |
US6400631B1 (en) * | 2000-09-15 | 2002-06-04 | Intel Corporation | Circuit, system and method for executing a refresh in an active memory bank |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08167703A (en) * | 1994-10-11 | 1996-06-25 | Matsushita Electric Ind Co Ltd | Semiconductor device, manufacture thereof, memory core chip and memory peripheral circuit chip |
JPH09293015A (en) * | 1996-04-24 | 1997-11-11 | Mitsubishi Electric Corp | Memory system and semiconductor storage device used therein |
JPH1115742A (en) * | 1997-06-19 | 1999-01-22 | Kofu Nippon Denki Kk | Memory refresh control circuit |
US6222785B1 (en) * | 1999-01-20 | 2001-04-24 | Monolithic System Technology, Inc. | Method and apparatus for refreshing a semiconductor memory using idle memory cycles |
JP2002007308A (en) * | 2000-06-20 | 2002-01-11 | Nec Corp | Memory bus system and connecting method for signal line |
US6925086B2 (en) * | 2000-12-12 | 2005-08-02 | International Business Machines Corporation | Packet memory system |
-
2003
- 2003-09-29 US US10/674,981 patent/US7353329B2/en not_active Expired - Fee Related
-
2004
- 2004-08-23 TW TW093125383A patent/TWI252487B/en not_active IP Right Cessation
- 2004-09-29 JP JP2006528329A patent/JP2007507056A/en active Pending
- 2004-09-29 CN CNB2004800271402A patent/CN100472492C/en not_active Expired - Fee Related
- 2004-09-29 WO PCT/US2004/032039 patent/WO2005033959A1/en active Application Filing
- 2004-09-29 EP EP04785279A patent/EP1668524A1/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5689677A (en) * | 1995-06-05 | 1997-11-18 | Macmillan; David C. | Circuit for enhancing performance of a computer for personal use |
US5859809A (en) * | 1996-12-31 | 1999-01-12 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device of daisy chain structure having independent refresh apparatus |
WO1999030240A1 (en) * | 1997-12-05 | 1999-06-17 | Intel Corporation | Memory system including a memory module having a memory module controller |
US20010008496A1 (en) * | 1999-01-20 | 2001-07-19 | Wingyu Leung | Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory |
US6400631B1 (en) * | 2000-09-15 | 2002-06-04 | Intel Corporation | Circuit, system and method for executing a refresh in an active memory bank |
Also Published As
Publication number | Publication date |
---|---|
TW200527427A (en) | 2005-08-16 |
CN1853175A (en) | 2006-10-25 |
CN100472492C (en) | 2009-03-25 |
US20050071543A1 (en) | 2005-03-31 |
US7353329B2 (en) | 2008-04-01 |
EP1668524A1 (en) | 2006-06-14 |
TWI252487B (en) | 2006-04-01 |
JP2007507056A (en) | 2007-03-22 |
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