WO2007028109A3 - Methods and apparatus of stacking drams - Google Patents

Methods and apparatus of stacking drams Download PDF

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Publication number
WO2007028109A3
WO2007028109A3 PCT/US2006/034390 US2006034390W WO2007028109A3 WO 2007028109 A3 WO2007028109 A3 WO 2007028109A3 US 2006034390 W US2006034390 W US 2006034390W WO 2007028109 A3 WO2007028109 A3 WO 2007028109A3
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WO
WIPO (PCT)
Prior art keywords
methods
constructed
memory
chips
drams
Prior art date
Application number
PCT/US2006/034390
Other languages
French (fr)
Other versions
WO2007028109A2 (en
Inventor
Suresh Rajan
Michael Smith
David Wang
Original Assignee
Metaram Inc
Suresh Rajan
Michael Smith
David Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Metaram Inc, Suresh Rajan, Michael Smith, David Wang filed Critical Metaram Inc
Priority to JP2008529353A priority Critical patent/JP5242397B2/en
Priority to GB0803913A priority patent/GB2444663B/en
Priority to DE200611002300 priority patent/DE112006002300B4/en
Priority to KR1020087005172A priority patent/KR101303518B1/en
Publication of WO2007028109A2 publication Critical patent/WO2007028109A2/en
Publication of WO2007028109A3 publication Critical patent/WO2007028109A3/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates

Abstract

Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
PCT/US2006/034390 2005-09-02 2006-09-01 Methods and apparatus of stacking drams WO2007028109A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008529353A JP5242397B2 (en) 2005-09-02 2006-09-01 Method and apparatus for stacking DRAM
GB0803913A GB2444663B (en) 2005-09-02 2006-09-01 Methods and apparatus of stacking drams
DE200611002300 DE112006002300B4 (en) 2005-09-02 2006-09-01 Device for stacking DRAMs
KR1020087005172A KR101303518B1 (en) 2005-09-02 2006-09-01 Methods and apparatus of stacking drams

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71381505P 2005-09-02 2005-09-02
US60/713,815 2005-09-02

Publications (2)

Publication Number Publication Date
WO2007028109A2 WO2007028109A2 (en) 2007-03-08
WO2007028109A3 true WO2007028109A3 (en) 2008-01-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/034390 WO2007028109A2 (en) 2005-09-02 2006-09-01 Methods and apparatus of stacking drams

Country Status (6)

Country Link
US (6) US7379316B2 (en)
JP (3) JP5242397B2 (en)
KR (1) KR101303518B1 (en)
DE (2) DE112006004263B4 (en)
GB (1) GB2444663B (en)
WO (1) WO2007028109A2 (en)

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US7379316B2 (en) 2008-05-27
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