WO2008002645A2

WO2008002645A2 - Memory device and method for selective write based on input data value

Info

Publication number: WO2008002645A2
Application number: PCT/US2007/015022
Authority: WO
Inventors: Christopher Lee; Thinh Tran; Joseph Tzou
Original assignee: Cypress Semiconductor Corporation
Priority date: 2006-06-28
Filing date: 2007-06-27
Publication date: 2008-01-03
Also published as: WO2008002645A3

Abstract

A memory device can include at least one data input node, a memory cell array having a plurality of addressable locations that store data values, and a write data path. A write data path can couples only write data having one predetermined logic value from the at least one data input node to the memory cell array.

Description

MEMORY DEVICE AND METHOD FOR SELECTIVE WRITE BASED ON INPUT DATA VALUE

TECHNICAL FIELD

The present invention relates generally to integrated circuit devices, and more particularly to write data paths of memory devices.

Conventional memory devices can store data values at addressable locations for subsequent retrieval in a read operation. Conventional memory devices can include random access memories (RAMs), such as static RAMs (SRAMs), dynamic RAMs (DRAMs), and pseudo DRAMs, as but a few examples. Conventional memories can also include read-only- memories (ROMS), such as electrically erasable and programmable ROMs (EEPROMs), including "flash" EEPROMs that can erase on a sector by sector basis.

One application for RAMs, such as SRAMs, can be the capture of error data in a testing system. To better understand various features of the below embodiments, a conventional testing system will first be described.

Referring to FIGS. 13A to 13D, the operation of a conventional testing system 1300 is shown in a series of block diagrams. Conventional testing system 1300 can include an error data RAM 1302 and an application specific integrated circuit (ASIC) 1304. Error data RAM 1302 can be used to store error data provided by ASIC 1304, and can include a number of addressable storage locations (AO to An). Each bit stored by error data RAM 1302 can correspond to a tested location or device. As each of a sequence of tests is performed, test results can be acquired and then written to the appropriate location. In the example shown, an error test result is indicated by a "1". Thus, any location/device failing any of the tests can be shown by a "1" in error data RAM 1302.

FIG. 13 A shows system 1300 after a test has been performed. New error data 1306 can be received by ASIC 1304. As shown, one bit location includes a "1" indicating an error has been detected. It is assumed that new error data needs to be stored at location A2 of error data RAM 1302.

As shown in FIG. 13B, to record the newly acquired error data 1306, ASIC 1304 first retrieves old error data 1308 for the corresponding location. This can include ASIC 1304 issuing a read command to error data RAM 1302 with a read address of A2. As shown in FIG. 13C, ASIC 1304 can perform a logical bitwise OR operation on the new error data 1306 and old error data 1308 to create modified error data 1310. Thus, modified error data 1310 can reflect all current test data for the corresponding locations/devices.

As shown in FIG. 13D, modified error data 1310 can be stored at location A2, to update all error data corresponding to the location. This can include ASIC 1304 issuing a write command to error data RAM 1302 with at a write address of A2, and with the modified error data 1310 as the write data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. IA to 1C are block diagrams of memory devices according to embodiments of the invention.

FIGS. 2A to 2D are block schematic diagrams showing the operation of a write data path according to other embodiments.

FIGS. 3 A to 3D are a sequence of block schematic diagrams showing systems according to embodiments.

FIGS. 4 A to 4C are block schematic diagrams showing write data paths according to other embodiments.

FIG. 5 is a block schematic diagram showing a write data path according to another embodiment.

FIG. 6 is a block schematic diagram showing a write data path according to another embodiment.

FIG. 7 is a block schematic diagram showing a "late" write data path according to another embodiment.

FIG. 8 is a memory device according to an embodiment.

FIG. 9 is a block diagram showing a mode setting arrangement according to an embodiment.

FIG. 10 is a block diagram showing a mode setting arrangement according to another embodiment.

FIG. 11 is a timing diagram showing a mode setting operation according to an embodiment.

FIG. 12 is a timing diagram showing another mode setting operation according to smother embodiment.

FIGS. 13A to 13D are block schematic diagrams of a conventional testing system.

DETAILED DESCRIPTION

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show memory devices and methods that allow for write operations that depend upon the data value being written.

A memory device according to a first embodiment is shown in FIG. IA and designated by the general reference character 100. A memory device 100 can include a memory cell array 102 and a write data path circuit 104. A memory cell array 102 can have a number of storage locations accessible by addresses. A memory cell array 102 can include memory cells arranged in rows and columns, preferably random access memory (RAM) cells, even more preferably static RAM cells. It is understood that array 102 can also include conventional memory array circuits, such as row and column decoders, sense amplifiers, and word line drivers, as but a few examples.

A write data path circuit 104 provides a path for writing data into locations of memory cell array 102. In the particular example of FIG. 1, write data path circuit 104 can receive data input values by way of "N" data inputs Dl — DN. A write data path circuit 104 is shown in FIGS. IB and 1C in more detail.

Referring now to FIG. IB, a write data path circuit 104 can include a number of write data paths 106-1 to 106-N. Each write data path (106-1 to 106-N), unlike a conventional path, can allow only one type of data value to pass through to a selected storage location within memory cell array 102. In the particular example shown, each write data path (106-1 to 106- N) allows only a data value of logic "1" to be applied to an array. Such a feature may be advantageous in error capture memory devices, as will be described in more detail below. Referring now to FIG. 1C, a write data path circuit 104' like that of FIG. IB can include a number of write data paths 1O6'-1 to 1O6'-N. However, unlike the example of FIG. 1C, each write data path (1O6'-1 to 106'-N) can allow only a data value of logic "0" to be applied to an array.

In this way, a memory device can include write data paths that are enabled in response to one type of data value (e.g., logic 1 or logic 0) and disabled in response to another type of data value (e.g., logic 0 or logic 1). Referring now to HGS. 2 A and 2B, a write data path circuit according to a second embodiment is designated by the general reference character 204, and shown in a sequence of block schematic diagrams. Like write data path circuit 104 of FIG. IB, the write data path circuits of FIGS. 2 A and 2B can include N write data paths 206-1 to 206-N. However, unlike the arrangement of FIG. IB, each of write data paths (206-1 to 206-N) can be configurable between at least two modes established by mode indication ECR.

FIG. 2A shows a first mode (ECRl = HI). In a first mode, write data paths (206-1 to 206-N) can operate as shown in FIG. IB. That is, first logic values (in this case 1), are allowed to be applied to a memory cell array (and hence written to a storage location), while second logic values (in this case 0), are not allowed to be applied to a memory cell array (and hence not written to a storage location).

FIG. 2B shows a second mode (ECRl = LOW). In a second mode, write data paths (206-1 to 206-N) can operate in a conventional fashion. That is, data values are applied to a memory cell array and written to a storage location regardless of logic value. FIGS. 2C and 2D show a write data path circuit like that of 104' of FIG. 1C. However, the write data path circuit 204' of FIGS. 2C and 2D, like that of FIGS. 2A and 2B, can be configurable between at least two modes established by mode indication ECRO to write only logic 0 values to an array.

In this way, a memory device write data path can be configurable between a "write only one logic value" mode, and a conventional mode.

Referring now to FIGS. 3A and 3B, a testing system 300 according to one embodiment is shown in a series of block diagrams. Testing system 300 can include a memory device 302 and an application specific integrated circuit (ASIC) 304. Memory device 302 can be memory device that includes write data paths according to any of the embodiments shown herein. Memory device 302 can include a number of addressable locations (AO to An).

KG. 3A essentially follows FIG. 13A, showing system 300 after a test has been performed. New error data 306 can be received by ASIC 304 for storage at an address A2. Error data 306 includes a "1" indicating an error has been detected.

As shown in FIG. 13B, to record the newly acquired error data 306, ASIC 304 can execute a single "write only one logic value" operation, to write the data bit having the logic 1 to the corresponding bit location at address A2. This is in sharp contrast to the conventional arrangement of FIGS. 13 A to 13D, that includes a read operation, a logic operation (logic OR), and write operation.

FIGS. 3C and 3D show a testing system 300', like that shown in FIGS. 3 A and 3B, but with an arrangement that writes only "0" values rather than "1" values.

In this way, a memory device having a write data path according to the embodiments can provide for advantageously fast error data writing operations.

Referring now to FIGS. 4A to 4C, write data path according to various particular embodiments are shown in schematic diagrams.

Referring now to FIG. 4A, a write data path is shown in a schematic diagram and designated by the general reference character 400. A write data path 400 can receive an input write data value (din[n]) and generate complementary values (wdin[n] and wdin#[n]). Thus, write data path 400 can include a non-inverting data path 402 and an inverting data path 404. Non-inverting data path 402 can include inverters 140 and 142 in series, and thus pass input data value din[n] as write data value wdin[n]. Inverting data path 404 can include control logic G40, which in this example can be a two-input NOR gate. NOR gate G40 can receive input data value din[n] as one input value, and a control signal ECRl as another input value.

In the arrangement of FIG. 4A, when control signal ECRl is inactive (low in this example), write data path 400 drives data according to a received input value din[n], operating as a conventional write path. Similarly, when control signal ECRl is active (high in this example), and a received input data value din[n] is high, write data path 400 can drive write data values wdin[n] and wdin#[n] high and low, respectively. However, when control signal ECRl is active and an input value din[n] is low, both values wdin[n] and wdin#[n] can be driven low, which can prevent a write operation

FIG. 4B shows another example of a write path, like that of FIG. 4A. However, in this example the writing of "1" data values can be prevented.

Referring now to FIG. 4B, a write data path is shown in a schematic diagram and designated by the general reference character 430. A non-inverting data path 432 and can include an inverter 143 and control logic G43, which in this case can be a two-input NOR gate. NOR gate G43 can receive input data value din[n] via inverter 143 as one input, and a control signal ECRO as another input value. An inverting data path 434 can include inverter 145. In this arrangement, when control signal ECRO is active and input value din[n] is high, both values wdin[n] and wdin#[n] can be driven low, which can prevent a write operation. While FIG.4A shows an arrangement that is configurable to write only logic "1", and the arrangement of FIG. 4B is configurable to write only logic "0", other embodiments can accommodate either such mode. One example of such an arrangement is shown in FIG.4C.

Referring now to FIG.4C, a write data path is shown in a schematic diagram and designated by the general reference character 460. A non-inverting data path 462 can have the same construction as non-inverting path 432 of FIG. 4B. Inverting data path 464 can have the same construction as non-inverting path 404 of FIG. 4A.

In the arrangement of FIG.4C, when both control signals ECRl and ECRO are inactive (low in this example), output value wdin[n] is driven according to input value din[n], while output value wdin#[n] is driven according to the complement of input value din[n]. However, when control signal ECRl is active (high in this example) and ECRO is inactive, writes for an input data value of "0" are prevented by driving both output values wdin[n]/wdin#[n] low. Similarly, when control signal ECRO is active and ECRl is inactive, writes for an input data value of "1" are prevented by driving both output values wdin[n]/wdin#[n] low.

In this way, a write data path can be prevented from writing a particular type of data value to a storage location.

Referring now to FIG. 5, a write data path according to another particular embodiment is shown in a schematic diagram, and designated by the general reference character 500. A write data path 500 can include a non-inverting data path 502, an inverting data path 504, an input register 506, and bit line pull-down circuit 508. FIG. 5 can differ from the embodiment of FIG. 4C in that an input data value (din[n]) can be clocked into the write data path by input register 506 according to a clock signal CLK. Thus, an input register 506 can be situated between a data input 510 and data paths (502 and 504). In addition, in FIG. 5, an input data value can be clocked through non-inverting and inverting data paths (502 and 504) according to a write clock signal WRCLK. Thus, non-inverting data path 502 can include logic G52 to selectively allow data to pass through according to signal WRCLK. Similarly, inverting data path 504 can include logic G56 to selectively allow data to pass through according to signal WRCLK. In the example of FIG. 5, logic G52/G56 can be two- input NAND gates with one input connected to receive write clock signal WRCLK, and another input connected to receive an input data value.

FIG. 5 also shows one particular write arrangement in which a write data value can be applied by pulling down a bit line BL or complementary bit line BL# according to write data values output from data paths 502 and 504, respectively. In particular, a bit line pull-down circuit 508 can include a transistor M50 having a source-drain path connected between bit line BL# and a low potential, and a transistor M52 having a source-drain path connected between bit line BL and a low potential. A gate of transistor M50 can be connected to the output of non-inverting data path 502. A gate of transistor M52 can be connected to the output of inverting data path 504.

In the arrangement of FIG. 5, to write a data value "1", transistor M50 can be turned on, pulling bit line BL# low, while transistor M52 can be off, maintaining bit line BL at a high precharge level. Conversely, to write a data value "0", transistor M52 can be turned on, pulling bit line BL, while transistor M50 can be off, maintaining bit line BL# at a high precharge level. However, when the writing of either such value is to be prevented, both transistors M50 and M52 can be turned off.

In this way, data can be clocked into a write path, and selectively written according to the value of the data (e.g., logic 1 or 0), as well as according to a timing signal..

HG. 6 is a block schematic diagram of a write data path 600 according to yet another embodiment of the present invention. The embodiment of FIG. 6 can include some of the same sections as FIG. 5, thus like items are referred to by the same reference character, but with the digit "5" being replaced by the digit "6".

The embodiment of FIG. 6 can differ from that of FIG. 5 in that is can include a decode section 660. A decode section 660 can selectively disable outputs of data paths 602 and 604 according to a decode signal dec[m]. In FIG. 6, decode section 660 can include path enable circuit M64, and a path disable circuit M66. Path enable circuit M64 can provide a low impedance or high impedance path between the output of non-inverting data path 602 and pull-down circuit 608 according to decode signal dec[m]. Path disable circuit M66 can force an input to pull-down circuit 608 to a disable level (low in this example) according to decode signal dec[m]. In the particular example shown, path enable circuit M64 can be a transistor having a source-drain path connected between the output of non-inverting data path 602 and a gate of pull-down transistor M60. Path disable circuit M66 can be a transistor having a source-drain path connected between the gate of pull-down transistor M60, and a low potential. The gates of transistors M64 and M66 can receive the decode signal dec[m] via an inverter 162. Decode section 660 includes the same arrangement between inverting data path 604 and pull-down transistor M63 formed with transistors M68, M70 and inverter 164.

In this way, a write data path having a decoded path can be disabled according to a received write data value.

Referring now to FIG. 7, a write circuit according to another particular embodiment is shown in a block schematic diagram, and designated by the general reference character 700. A write circuit 700 can accommodate "late" write and "double late" write operations. In a late write operation, write data is held for a certain time period (e.g., one clock cycle) prior to being written into an array. Further, such held data can be output via a data output, for example in a read operation, if desired. Similarly, in a double late write operation, write data can be held for a longer period of time than a late write operation (e.g., two clock cycles) prior to being written into an array. Again, such held data can be output if desired for a read operation, or the like.

A write circuit 700 can include a data path 702, an enable path 704, a write data path 706, an input buffer 708, and a read data path 710. An input buffer 708 can receive a write data value DIN. Such value can be buffered and provided as an input to data path 702.

A data path 702 can include a register 712, and a data path multiplexer (MUX) 714. A data path MUX 714 can selectively output a data value from either register 710 or buffer 708 according to a write control signal WCTRL.

An enable data path 704 can include a register 716 and an enable path MUX 718. An enable data path 704 can passthrough an enable signal ECRO (enable only "0" writes), an enable signal ECRl (enable only "1" writes), or both such signals according to essentially the same timing as data path 702, which carries an accompanying input data value. Enable data path 704 can operate in the same general fashion as data path 702 to provide an enable signal(s) ECRO/1. However, enable signals ECRO/1 preferably arrive at data path 706 prior to input data value din[n].

Write data path 706 can take the form of any of the embodiments set forth above. Write data path 706 can receive an input data value din[n] and selectively prevent the writing of a "0" or "1" based on a received enable signal ECRO, ECRl, or both.

Referring still to FIG. 7, a read data path 710 can include a read MUX 720, and MUX control logic 722. Read MUX 720 can selectively choose between read data originating from a memory ceϊl array rdout[n] or data in data path 702. Control of such switching can be established by MUX control logic 722 that can determine when a read address matches the address of write data (ADD MATCH high), and the read data is "0".

In this way, a "write only one logic value" operation can be included with a late or double late write signal path.

Selected of the above embodiments have shown write data paths selectable between standard and "write only one logic value" modes according to a mode signal ECRO/1. Various approaches to providing such a signal will now be described.

Referring now to FIG. 8, a memory device is shown in a block schematic diagram and designated by the general reference character 800. A memory device 800 can include a memory cell array 802, a write driver 804, sense amplifiers 806, an input/output (I/O) circuit 808, control logic 810, a control register 812, and an address register 814. Alternatively, a memory device 800 can include a write mode circuit 816.

In one arrangement, a control register 812 can include a location for writing mode data for configuring the memory device 800 to operate in different modes. Three possible modes can include: a write only "1" mode, which can activate an enable signal ECRl; a write only "0" mode, which can activate an enable signal ECRO, or a "normal" operation that enables standard write operations. Such an arrangement can allow for easy switching between modes.

Referring still to FIG. 8, a memory device (e.g., 800) can be placed into a "write only one data value" mode without having the input of any signal values. For example, a write mode circuit 816 can provide a mode signal(s) ECRO/1 established by a hardware option. As a first example, a write mode circuit 816 can be "mask option". That is, one or more particular masks can be used when the device is manufactured than ensure a particular node is connected to a power supply, or otherwise is forced to have a certain level. As a second example, a write mode circuit 816 can include a fuse circuit that sets a node to a particular value based on a fusible link (or antifuse structure) that can be forced to an electrical short or open in a manufacturing step. As a third example, a write mode circuit 816 can include a nonvolatile memory cell programmable to a certain logic level that can establish the value of signal(s) ECRO/1.

Still further, a mode of a memory device (e.g., 800) can be established in a manufacturing step following the fabrication of the integrated circuit device. Two of the many possible examples are shown in FIGS. 9 and 10. ^ FIG. 9 shows how a "write only one logic value" mode can be established by a

"bonding" option. FIG. 9 shows a portion of an integrated circuit 900 that can include a memory device and/or write path according to any of the above embodiments. Integrated circuit 900 can include a number of bond pads, one of which is shown as 902, that provide electrical connections from the integrated circuit 900 to a packaging structure (e.g., bond wire, finger, "bump", etc.). One or more particular bond pads 902 can be connected to a predetermined level (e.g., VDD or VSS) and thus provide a desired mode signal ECR for use in the integrated circuit 900. In the particular example of FIG. 9, a predetermined level can be provided by bonding a bond pad to a power supply bus 904 of an integrated circuit package.

In this way, a "write only one logic value" mode can be established with a package bonding option, or the like.

FIG. 10 shows how a "write only one logic value" mode can be established by a pin option. FIG. 10 shows a portion of an integrated circuit package 1000 that can contain a memory device and/or write path according to any of the above embodiments. A package 1000 can include a number of external pins, one of which is shown as 1002 that provide electrical connections to the integrated circuit within package 1000. One or more particular pins (e.g., 1002) can be connected to a predetermined level (e.g., VDD or VSS) and thus provide a desired mode signal ECR for use in the integrated circuit contained by package 1000.

In this way, a "write only one logic value" mode can be established with a pin connection option, or the like.

Referring back to FIG. 8, a write mode circuit 816 may also include volatile circuits, such as storage registers. Even more particularly, write mode circuit 816 can include writable registers to allow dynamic switching between modes. One particular example of such an arrangement is shown in FIGS. 11 and 12.

Referring now to FIGS. 11 and 12, two examples of a mode setting operation are shown in a timing diagram. In the examples shown, a mode can be set by writing data values to a register (REGx). The register can be accessed by a predetermined combination of control signals 1100 and the application of particular data values (DQO and DQl). Of course, various other ways of programming registers are well known, and this particular arrangement should not be construed as limiting the invention to such a mode. FIG. 11 shows a mode setting operation 1102 that writes values to register REGx that sets in a mode to "Mode ECRl" that results in a signal ECRl being active (high in this example), and signal ECRO being inactive (low in this example). After such an operation, in a subsequent write operation 1104, a logic "1" value is written and a logic "0" value is not written.

FIG. 12 shows a mode setting operation 1202 that writes values to register REGx that switches from a "Mode ECRl" to a mode "Mode ECRO" that results in a signal ECRO being active (high in this example), and signal ECRl being inactive (low in this example). After such an operation, in a subsequent write operation 1204, a logic "0" value is written and a logic "1" value is not written.

Of course, the various examples shown above represent but a few of the many possible ways of setting a memory device into either a standard mode of "write only one logic value" mode.

Embodiments of the present invention are well suited to performing various other steps or variations of the steps recited herein, and in a sequence other than that depicted and/or described herein.

For purposes of clarity, many of the details of (subject matter) and the methods of designing and manufacturing the same that are widely known and are not relevant to the present invention have been omitted from the following description.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined as suitable in one or more embodiments of the invention.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention can be elimination of an element.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.

Claims

IN THE CLAIMS What is claimed is:

1. A memory device, comprising: at least one data input node; a memory cell array having a plurality of addressable locations that store data values; and a write data path that couples one predetermined logic value from the at least one data input node to the memory cell array and prevents another logic value from being coupled from the at least one data input node to the memory cell array.

2. The memory device of claim 1, wherein: the write data path couples only write data having the one predetermined logic value to the memory cell array in a first mode and couples write data at the at least one data input node to the. memory cell regardless of logic value in a second mode.

3. The memory device of claim 1, wherein: the one predetermined logic value is a logic 1.

4. The memory device of claim 1, wherein: the write data path comprises a first write data path coupled to the at least one data input node that drives a first write data output in response to a input data value, and a second write data path coupled to the at least one data input node that drives a second write data output in response to the input data value and the at least one mode signal.

5. The memory device of claim 4, further including: the data path comprises N clocked data stages, where N is at least 1; the enable data path comprising N clocked data value stages coupled to receive the at least one mode signal that indicates at least a first mode or a second mode.

The memory device of claim 5, further including: a late write multiplexer (MUX) having a first input coupled to an output of a first of the N clocked data stages, and a second input coupled to an input of the N clocked data stages, and a MUX control input coupled to receive a late write mode signal.

7. The memory device of claim 4, wherein: the first write data path and second write data path drive two write output nodes to complementary values when enabled.

8. The memory device of claim 4, wherein: the first and second write data paths drive the first and second write data outputs to the same logic value in response to a write enable clock signal.

9. The memory device of claim 1 , further including: a decode path coupled to the write data path that enables and disables a low impedance path to the memory cell array according to a decoder signal generated in response to a received memory address.

10. The memory device of claim 9, wherein: the write data path comprises a first write data path coupled to the at least one data input node that drives a first write data output in response to at least an input data value, and a second write data path coupled to the at least one data input node that drives a second write data output in response to the input data value and at least one mode signal; and the decode path comprises at least a first transistor having a source-drain path coupled between the first write data path and a first array input, and at least a second transistor having a source-drain path coupled between the second write data path and a second array input.

A memory device, comprising: a storage circuit having a plurality of addressable locations; a configuration circuit that generates at least one write mode signal according to at least one configuration value; and a write data path coupled to receive write data that prevents a writing of write data having one predetermined logic value according to the at least one write mode signal.

12. The memory device of claim 11, further including: a plurality of external connections to the memory device; and configuration circuit includes an input circuit electrically coupled to at least one of the external connections that generates the at least one write mode signal in response to a signal received at the at least oiie external connection.

13. The memory device of claim 12, wherein: the configuration circuit includes an addressable register that stores a value corresponding to the at least one write mode signal.

14. The memory device of claim 12, wherein: the input circuit drives the at least one write mode signal to a predetermined level in response to the at least one external connection being coupled to a power supply voltage level.

15. The memory device of claim 11 , wherein: the write data path includes a first path coupled to a data input node, a second path having a logic circuit coupled to the data input node and a second input coupled to the at least one mode signal.

16. A method of writing only one particular logic value to a memory cell array, comprising the steps of: receiving a plurality of write data values having one of at least two logic values; receiving a write address; writing a write data value to a storage location corresponding to the write address in response to at least the write data input value having a first predetermined logic value; and preventing the writing of the write data value to the storage location corresponding to the write address in response to at least the write data input value having a second predetermined logic value.

17. The method of claim 16, wherein: receiving the plurality of write data values includes receiving the write data values in parallel with one another on a plurality of data input lines.

18. The method of claim 16, wherein: the step of preventing the write data value from being written includes enabling a write data path in response to the write data value.

19. The method of claim 16, further including: writing the write data value includes writing the write data value in response to at least the write data input value and a first type mode indication; preventing the writing of the write data value includes preventing such a write in response to at least the write data input value and the first type mode indication; and writing the write data value to the storage location regardless of the logic value in response to a second type mode indication.

20. The method of claim 16, wherein: the first predetermined logic value is a logic one.