WO2008002645A3 - Memory device and method for selective write based on input data value - Google Patents

Memory device and method for selective write based on input data value Download PDF

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Publication number
WO2008002645A3
WO2008002645A3 PCT/US2007/015022 US2007015022W WO2008002645A3 WO 2008002645 A3 WO2008002645 A3 WO 2008002645A3 US 2007015022 W US2007015022 W US 2007015022W WO 2008002645 A3 WO2008002645 A3 WO 2008002645A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory device
input data
data value
selective write
write based
Prior art date
Application number
PCT/US2007/015022
Other languages
French (fr)
Other versions
WO2008002645A2 (en
Inventor
Christopher Lee
Thinh Tran
Joseph Tzou
Original Assignee
Cypress Semiconductor Corp
Christopher Lee
Thinh Tran
Joseph Tzou
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp, Christopher Lee, Thinh Tran, Joseph Tzou filed Critical Cypress Semiconductor Corp
Publication of WO2008002645A2 publication Critical patent/WO2008002645A2/en
Publication of WO2008002645A3 publication Critical patent/WO2008002645A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Abstract

A memory device can include at least one data input node, a memory cell array having a plurality of addressable locations that store data values, and a write data path. A write data path can couples only write data having one predetermined logic value from the at least one data input node to the memory cell array.
PCT/US2007/015022 2006-06-28 2007-06-27 Memory device and method for selective write based on input data value WO2008002645A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47694406A 2006-06-28 2006-06-28
US11/476,944 2006-06-28

Publications (2)

Publication Number Publication Date
WO2008002645A2 WO2008002645A2 (en) 2008-01-03
WO2008002645A3 true WO2008002645A3 (en) 2008-08-07

Family

ID=38846315

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/015022 WO2008002645A2 (en) 2006-06-28 2007-06-27 Memory device and method for selective write based on input data value

Country Status (1)

Country Link
WO (1) WO2008002645A2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349560A (en) * 1992-03-30 1994-09-20 Samsung Electronics Co., Ltd. Semiconductor memory device with improved bit line precharged circuits
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
US5761150A (en) * 1995-05-24 1998-06-02 Hitachi, Ltd. Synchronous memory with pipelined write operation
US6330202B1 (en) * 1999-11-12 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having write data line
US20020116587A1 (en) * 2000-12-22 2002-08-22 Modelski Richard P. External memory engine selectable pipeline architecture
US20030210334A1 (en) * 2002-05-13 2003-11-13 Atif Sarwari Integrated CMOS imager and microcontroller

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349560A (en) * 1992-03-30 1994-09-20 Samsung Electronics Co., Ltd. Semiconductor memory device with improved bit line precharged circuits
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
US5761150A (en) * 1995-05-24 1998-06-02 Hitachi, Ltd. Synchronous memory with pipelined write operation
US6330202B1 (en) * 1999-11-12 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having write data line
US20020116587A1 (en) * 2000-12-22 2002-08-22 Modelski Richard P. External memory engine selectable pipeline architecture
US20030210334A1 (en) * 2002-05-13 2003-11-13 Atif Sarwari Integrated CMOS imager and microcontroller

Also Published As

Publication number Publication date
WO2008002645A2 (en) 2008-01-03

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