WO2013095836A1

WO2013095836A1 - Systems and methods of performing a data save operation

Info

Publication number: WO2013095836A1
Application number: PCT/US2012/065862
Authority: WO
Inventors: Daniel Zvi YERUSHALMI; Yaniv Iarovici
Original assignee: Sandisk Technologies Inc.
Priority date: 2011-12-22
Filing date: 2012-11-19
Publication date: 2013-06-27
Also published as: EP2795453A1; US9092150B2; US20130166864A1

Abstract

A method includes determining, based on an indication from a host device operatively coupled to a data storage device that includes a controller, a non-volatile memory including a hibernate area, a volatile memory, a non-volatile memory interface, and a volatile memory interface, that the data storage device is to enter a low-power state. The method includes, in response to determining that the data storage device is to enter a low-power state, performing a data save operation. The data save operation bypasses the non-volatile memory interface and the volatile memory interface and copies data from the volatile memory of the data storage device to the hibernate area of the non-volatile memory of the data storage device.

Description

SYSTEMS AND METHODS OF PERFORMING A DATA SAVE OPERATION FIELD OF THE DISCLOSURE

The present disclosure is generally related to performing a data save operation. BACKGROUND Use of mobile devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users is widespread. However, power consumption of such mobile devices can quickly deplete a battery within the device. Many devices include one or more components that can enter a low-power mode when not in use. However, system memory includes information that is typically needed by the mobile device and that is lost when the memory loses power.

SUMMARY

Power savings may be achieved by a data storage device that is configured to enter a hibernation state (e.g., by shutting off power to a volatile memory in the data storage device). For example, power savings may be achieved by a data storage device that is configured to perform a data save operation that copies data from the volatile memory to a non-volatile memory in the data storage device. The data save operation may be performed in response to determining, based on an indication from a host device, that the data storage device is to enter a low-power state. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a first illustrative embodiment of a system to perform a data save operation that copies data from a volatile memory to a non- volatile memory;

FIG. 2 is diagram of a second illustrative embodiment of the system of FIG. 1;

FIG. 3 is a diagram of a third illustrative embodiment of the system of FIG. 1; FIG. 4 is a block diagram that illustrates a particular embodiment of receipt of hardware signals that indicate that a data storage device is to enter a low-power state; FIG. 5 is a block diagram that illustrates a particular embodiment of receipt of a hibernation instruction that indicates that a data storage device is to enter a low-power state;

FIG. 6 is a block diagram that illustrates a particular embodiment of receipt of a timer value exceeding a hibernation threshold to indicate that a data storage device is to enter a low-power state, where the timer value indicates an elapsed time since receipt of a request from the host device to access the volatile memory;

FIG. 7 is a block diagram that illustrates a particular embodiment of powering off the volatile memory of a data storage device; FIG. 8 is a block diagram that illustrates a particular embodiment of a data save operation that copies data from the volatile memory to a non-volatile memory of a data storage device;

FIG. 9 is a flow diagram illustrating a particular embodiment of a method of performing a data save operation that copies data from a volatile memory to a non- volatile memory of a data storage device; and

FIG. 10 is a flow diagram illustrating another particular embodiment of a method of performing a data save operation that copies data from a volatile memory to a nonvolatile memory of a data storage device.

DETAILED DESCRIPTION A data storage device performs a data save operation that copies data from a volatile memory in the data storage device to a non- volatile memory in the data storage device in response to determining, based on an indication from a host device, that the data storage device is to enter a low-power state (e.g., hibernation). Copying the data from the volatile memory to the non- volatile memory prevents loss of the data upon interruption of power to the volatile memory.

Systems and methods of performing a data save operation are disclosed. The data save operation copies data from a volatile memory of the data storage device to a nonvolatile memory of the data storage device in response to an indication from a host device that the data storage device is to enter a low-power state. Copying the data to the non- volatile memory prevents loss of the data upon interruption of power to the volatile memory.

Referring to FIG. 1, a particular illustrative embodiment of a system to perform a data save operation that copies data from a volatile memory to a non-volatile memory is depicted and generally designated 100. The system 100 includes a data storage device 102 coupled to a host device 130. The data storage device 102 includes a volatile memory 112 and a non- volatile memory 104 coupled to a controller 110. The volatile memory 112 may be a random access memory (RAM).

The host device 130 may be configured to provide data to be stored at the volatile memory 112 or at the non- volatile memory 104 or to request data to be read from the volatile memory 112 or from the non- volatile memory 104. For example, the host device 130 may include a mobile telephone, a music or video player, a gaming console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop computer, a notebook computer, or a tablet, any other electronic device, or any combination thereof.

The data storage device 102 is a multi chip package (MCP) device. The MCP device includes a non- volatile memory interface 194 to enable access to the non- volatile memory 104 by the host device 130 and a volatile memory interface 196 to enable access to the volatile memory 112 by the host device 130. The data storage device 102 is coupled to the host device 130 via a non- volatile memory bus 134 and a random access memory bus 136. The non- volatile memory bus 134 is coupled to the nonvolatile memory interface 194 and the random access memory bus 136 is coupled to the volatile memory interface 196. The data storage device 102 may provide non- volatile storage and volatile storage to the host device 130 via the non- volatile memory bus 134 and the random access memory bus 136, respectively.

The non- volatile memory 104 may be a non- volatile memory of a flash device, such as a NAND flash device, a NOR flash device, or any other type of flash device. The nonvolatile memory 104 includes a hibernate area 106. The hibernate area 106 may be a physical partition in the non- volatile memory 104, a dedicated range of storage blocks in the non- volatile memory 104, or a separate storage device, as illustrative examples. The hibernate area 106 may be configured to store data 116 that has been copied from the volatile memory 112 to the hibernate area 106 of the non- volatile memory 104.

The controller 110 controls operations of the non- volatile memory 104 and the volatile memory 112. For example, the controller 110 may include a flash controller or may be coupled to a separate flash controller. The controller 110 may be configured, upon receiving an instruction from the host device 130, to instruct the volatile memory 112 or the non- volatile memory 104 to store data or to instruct the volatile memory 112 or the non- volatile memory 104 to read data.

The controller 110 may be configured to enter a hibernation or other low-power state, upon receiving an instruction from the host device 130. For example, the controller 110 may be configured to determine, based on an indication 118 received from the host device 130, that the data storage device 102 is to enter a low-power state. The controller 110 may receive a power event signal from the host device 130 indicating a sleep state or a power off state, as described with respect to FIG. 4. As another example, the controller 110 may receive a hibernation instruction from the host device 130 indicating a hibernation state, as described with respect to FIG. 5, or may detect a period of inactivity, as described with respect to FIG. 6. Alternatively, the controller 110 may be configured to enter a hibernation or other low-power state independent of any instructions from the host device 130. In response to determining that the data storage device 102 is to enter the low-power state, the controller 110 may perform a data save operation 114 that bypasses the nonvolatile memory interface 194 and the volatile memory interface 196 and that copies the data 116 from the volatile memory 112 to the hibernate area 106 of the non- volatile memory 104. Copying the data 116 from the volatile memory 112 to the hibernate area 106 of the non- volatile memory 104 prevents loss of the data 116 upon interruption of power to the volatile memory 112. To illustrate, the data save operation 114 may include copying the data 116 from the volatile memory 112 to the controller 110, and writing the data 116 from the controller 110 to the hibernate area 106 of the non- volatile memory 104 via the bus 150. Upon completion of the data save operation 114, an indication 120 may be sent to the host device 130 that the data storage device 102 is prepared for interruption of power supplied by the host device 130. During operation, while the data storage device 102 is operatively coupled to the host device 130, the host device 130 may send read requests and/or write requests to access the non- volatile memory 104 and to access the volatile memory 112. The controller 110 is configured to process the read requests and the write requests. The host device 130 may send the indication 118 that the data storage device 102 is to enter the low-power state. In response to determining, based on the indication 118, that the data storage device 102 is to enter the low-power state, the controller 110 may perform the data save operation 114 that bypasses the non- volatile memory interface 194 and the volatile memory interface 196 and copies the data 116 from the volatile memory 112 to the non- volatile memory 104. For example, the data 116 may be copied from the volatile memory 112 to the hibernate area 106 of the non- volatile memory 104 via a dedicated bus, such as described with respect to FIG. 3, or via multiple internal buses, such as described with respect to FIG. 2. Upon completion of the data save operation 114, the controller 110 may send the indication 120 to the host device 130 indicating that the data storage device 102 is prepared for interruption of power supplied by the host device 130. Alternatively, or in addition, the controller 110 may be configured, upon completion of the data save operation 114, to power off the volatile memory 112 while maintaining power to the controller 110, such as described with respect to FIG. 7. Upon completion of the data save operation 114, the controller 110 may cause the data storage device 102 to enter the low-power state.

After the data storage device 102 enters the low-power state, the controller 110 may be configured to cause the data storage device 102 to exit the low-power state. For example, the controller 110 may be configured to perform a data restore operation 115. The data restore operation 115 may include copying stored data from the non- volatile memory 104 to the volatile memory 112 to restore a memory image of the volatile memory 112. The stored data may be copied from the non- volatile memory 104 to the controller 110 and then from the controller 110 to the volatile memory 112, as described in further detail with respect to FIG. 2. Alternatively, the stored data may be copied from the non- volatile memory 104 to the volatile memory 112 via a hibernation bus, as described in further detail with respect to FIG. 3. In implementations where the volatile memory 112 is powered off while the controller 110 remains operational, powering off the volatile memory 112 reduces overall power consumption of the data storage device 102. Performing the data save operation 114 enables the data storage device 102, upon power up, to more quickly revert to a state that the data storage device 102 was in prior to entering the low-power state because the data 116 copied from the volatile memory 112 to the non- volatile memory 104 may be readily available to the host device 130 upon power up and without requiring participation of the host device in the data storage and the data retrieval related to the data save operation 114. Referring to FIG. 2, a second illustrative embodiment of the system of FIG. 1 is depicted and generally designated 200. The system 200 includes the data storage device 102 coupled to the host device 130. The data storage device 102 includes the nonvolatile memory 104, the hibernate area 106, the controller 110, and the volatile memory 112. The host device 130 includes an application processor 230 coupled to the non- volatile memory (NVM) bus 134. The application processor 230 is also coupled to the random access memory (RAM) bus 136. The host device 130 may be coupled to the data storage device 102 via the NVM bus 134 and the RAM bus 136. The application processor 230 may communicate with the non- volatile memory 104 via the NVM bus 134. The application processor 230 may communicate with the volatile memory 112 via the RAM bus 136 and the controller 110.

The controller 110 may provide an interface between the RAM bus 136 and the volatile memory 112. The controller 110 may translate addressing from the application processor 230 to RAM addressing. The controller 110 may also be configured to receive power event signals 220 from the host device 130. The power event signals 220 may include one or more hardware signals indicating a sleep state of the data storage device 102 or a power off state of the data storage device 102. The controller 110 may be configured to detect receipt of the power event signals 220 from the host device 130 and, based on the power event signals 220, determine that the data storage device 102 is to enter a low-power (e.g., sleep or power off) state. In response to determining that the data storage device 102 is to enter the low-power state, the controller 110 may perform the data save operation 114 of FIG. 1. The controller 110 may be configured to initiate data transfer between the volatile memory 112 and the non- volatile memory 104 by passing data from the volatile memory 112 through the controller 110 to the hibernate area 106 of the non- volatile memory 104. To illustrate, the controller 110 may be configured to initiate a read operation to read data from the volatile memory 112, to encode the read data for storage at the hibernate area 106 (e.g., error correction coding (ECC) encoding), and to write the encoded data to the hibernate area 106 of the nonvolatile memory 104 via the bus 150.

During operation, while the data storage device 102 is operatively coupled to the host device 130, the host device 130 may send the power event signals 220 indicating that the data storage device 102 is to enter the low-power state (e.g., indicating a sleep state of the data storage device 102 or a power off state of the data storage device 102). In response to determining, based on the power event signals 220, that the data storage device 102 is to enter the low-power state, the controller 110 may perform the data save operation 114 that copies the data 116 from the volatile memory 112 to the non- volatile memory 104.

The controller 110 may be configured to access a page loading table 206 that is stored in the hibernate area 106 and to use the page loading table 206 to determine an order of data retrieval upon exiting the low-power state. For example, the page loading table 206 may indicate a loading order of memory pages to be copied from a volatile memory image stored in the hibernate area 106 to the volatile memory 112. The controller 110 may incorporate or use a memory management unit to determine the loading order and may maintain the indication of the loading order in the page loading table 206.

In implementations where the volatile memory 112 is powered off while the controller 110 remains operational, powering off the volatile memory 112 reduces overall power consumption of the data storage device 102. Performing the data save operation 114 enables the data storage device 102, upon power up, to more quickly revert to a state that the data storage device 102 was in prior to entering the low-power state. The data 116 copied from the volatile memory 112 to the non- volatile memory 104 may be readily available to the application processor 230 upon power up and without requiring participation of the application processor 230 in the data storage and the data retrieval. Referring to FIG. 3, a third illustrative embodiment of the system of FIG. 1 is depicted and generally designated 300. The system 300 includes the data storage device 102 coupled to the host device 130. The host device 130 includes the application processor 230 coupled to the non- volatile memory bus 134 and coupled to the RAM bus 136. The data storage device 102 includes the controller 110, the non- volatile memory 104, the hibernate area 106, the page loading table 206, and the volatile memory 112. The data storage device 102 includes a hibernate data bus 312 to enable data transfer between the non- volatile memory 104 and the volatile memory 112 to bypass the controller 110.

The controller 110 is coupled to the hibernate data bus 312, and the hibernate data bus 312 connects the non- volatile memory 104 and the volatile memory 112. The controller 110 may be configured to detect receipt of the power event signals 220 from the host device 130 and to determine, based on the power event signals 220, that the data storage device 102 is to enter the low-power state. The controller 110 may be configured to perform the data save operation by generating a first bus control signal 314 (e.g., a signal, a command, etc.) to cause the hibernate data bus 312 to access data from the volatile memory 112 and to generate a second bus control signal 316 (e.g., a signal, a command, etc.) to cause the hibernate data bus 312 to send the data to the hibernate area 106 of the non- volatile memory 104. The page loading table 206 may be accessed by the controller 110 and used to determine a loading order of memory pages from a volatile memory image stored in the hibernate area 106 to the volatile memory 112 upon wakeup from the low-power state.

Using the hibernate data bus 312 may be faster for the data save operation or the data restore operation as compared to FIG. 2. For example, the controller 110 may be coupled to the non- volatile memory 104 via a bus and to the volatile memory 112 via another bus, such as illustrated in FIG. 2. Data transfer between the non-volatile memory 104 and the controller 110 and between the controller 110 and the volatile memory 112, as described with respect to FIG. 2, may introduce additional latency as compared to data transfer between the non- volatile memory 104 and the volatile memory 112 via the hibernate data bus 312. As a result, entering the low-power state and/or exiting the low-power state may be performed more quickly as compared to the system of FIG. 2. FIGS. 4-6 are examples of different indications that may be sent from a host device to a data storage device to indicate that the data storage device is to enter a low-power state, such as the indication 118 sent by the host device 130 of FIG. 1 to the controller 106 to indicate that the data storage device 102 of FIG. 1 is to enter the low-power state. For example, referring to FIG. 4, a diagram 400 illustrates receipt of hardware signals 402. The diagram 400 includes the controller 110 configured to receive the hardware signals 402 from the host device 130 at a hardware signal detection circuit 404. The hardware signals 402 may indicate a sleep state or a power off state. For example, the hardware signals 402 may be compatible with the advanced configuration and power interface (ACPI) specification for device configuration and power management, such as the Advanced Configuration and Power Interface Specification, Revision 5.0, released November 23, 2011.

The controller 110 may be configured to, in response to determining that the data storage device 102 is to enter the low-power state in response to receiving the hardware signals 402, perform the data save operation 114 that copies data from the volatile memory 112 to the non- volatile memory 104. After the data save operation 114 has completed, the data storage device 102 may enter a hibernation state. For example, the data storage device 102 may enter the hibernation state automatically after completing the data save operation 114. As another example, the hardware signals 402 may cause the data storage device 102 to enter the hibernation state. For example, the hardware signals 402 may indicate a sleep state, where the sleep state includes the hibernation state. The hardware signal detection circuit 404 may detect the hardware signals 402, may cause the data save operation 114 to be performed, and may cause the controller 110 to instruct the data storage device 102 to enter the hibernation state after the data save operation 114 has completed.

Referring to FIG. 5, a diagram 500 illustrates receipt of a hibernation instruction 502 from the application processor 230 of the host device 130 at a hibernation instruction detector 504 of the controller 110 of FIG. 1, FIG. 2, or FIG. 3. The hibernation instruction 502 may indicate the hibernation state. The controller 110 may be configured to, in response to determining that the data storage device 102 is to enter the low-power state in response to receiving the hibernation instruction 502, perform the data save operation 114 that copies data from the volatile memory 112 to the non- volatile memory 104. After the data save operation 114 has completed, the data storage device 102 may enter the hibernation state. For example, the hibernation instruction detector 504 may detect the hibernation instruction 502, may cause the data save operation 114 to be performed, and may cause the controller 110 to instruct the data storage device 102 to enter the hibernation state after the data save operation 114 has completed.

Referring to FIG. 6, a diagram 600 illustrates receipt of a request to access the volatile memory 112, such as a volatile memory access request 602. The controller 110 may be configured to determine that the data storage device 102 is to enter a low-power state by determining that an elapsed time since receipt of a most recent volatile memory access request 602 from the host device 130 to access the volatile memory 112 has exceeded a threshold.

For example, a volatile memory inactivity timer 604 may be a running timer that is reset each time a volatile memory access request 602 is received. A value of the volatile memory inactivity timer 604 may be compared to a threshold, such as a hibernation threshold 606. Based on the comparison between the inactivity timer 604 and the hibernation threshold 606, the data save operation 114 may be executed. For example, if the value of the volatile memory inactivity timer 604 exceeds the hibernation threshold 606 (e.g., the elapsed time since receipt of the volatile memory access request 602 to access the volatile memory 112 has exceeded an inactivity limit), the data save operation 114 may be executed.

After the data save operation 114 has completed, the data storage device 102 may enter the hibernation state. For example, the data storage device 102 may enter the hibernation state automatically after the data save operation 114 has completed and without instruction or intervention from the host device 130. As a result of

autonomously entering the hibernation state, a power saving benefit may be provided to host devices that may not support hibernation. In addition, by performing the data save operation 114 without intervention from an application processor of the host device, a processing load of the application processor of the host device is reduced as compared to an implementation where the host device directs the data transfer from volatile memory to non- volatile memory.

Referring to FIG. 7, a diagram 700 illustrates an embodiment of the controller 110 of FIGs. 1-3 configured to power off the volatile memory 112. The controller 110 may be configured to execute the data save operation 114. The controller 110 may be configured, upon completion of the data save operation 114, to power off the volatile memory 112 while maintaining power to the controller 110. For example, a power control circuit 702 for the volatile memory may be configured to detect that the data save operation 114 has completed. To illustrate, the power control circuit 702 for the volatile memory may include an input coupled to receive a result value that is generated by the data save operation 114. Upon detecting completion of the data save operation 114, the power control circuit 702 for the volatile memory may cause the controller 110 to interrupt a power supply to the volatile memory 112. As a result, the controller 110 may power off the volatile memory 112 while maintaining power to the controller 110. Referring to FIG. 8, a diagram 800 illustrates a data save operation that copies data from the volatile memory 112 to the non- volatile memory 104. The volatile memory 112 includes a memory image 802 including multiple memory portions 804, such as representative memory portions 810 and 812. The memory image 802 may include a copy of data in at least a portion of the volatile memory 112. Each particular memory portion of the multiple memory portions 804 may have a change indicator 806 that indicates whether the particular memory portion has been modified since a most recent data restore operation. For example, the data save operation 114 may cause the memory image 802 of the volatile memory 112 to be stored in the non-volatile memory 104. However, if a portion of the memory image 802 has not changed since a last save to the non- volatile memory 104, the portion need not be re-saved to the non- volatile memory 104. The data save operation 114 may selectively copy one or more of the memory portions 804 of the volatile memory 112 to the non- volatile memory 104 based on whether one or more of the change indicators 806 indicates that one or more of the memory portions 804 have been modified since a most recent data restore operation. For example, a change indicator value of "1" in the memory portion 810 may indicate that the memory portion 810 has been modified since a most recent data restore operation. Based on the indication that the memory portion 810 has been modified since a most recent data restore operation, the memory portion 810 may be selectively copied from the volatile memory 112 to the non- volatile memory 104 during the data save operation 114. Similarly, a change indicator value of "1" in the memory portion 812 may indicate that the memory portion 812 has been modified since a most recent data restore operation, and based on the indication, the memory portion 812 may be selectively copied from the volatile memory 112 to the non- volatile memory 104 during the data save operation 114. A change indicator value of "0" in one or more of the memory portions 804 may indicate that the one or more memory portions 804 have not been modified since a most recent data restore operation. In that case, the memory portions 804 having a change indicator value of "0" may not be copied from the volatile memory 112 to the non- volatile memory 104 during the data save operation 114.

By selectively copying data that has been modified since a most recent data restore operation from the volatile memory 112 to the non- volatile memory 104 and not copying data that has not been modified since the most recent data restore operation from the volatile memory 112 to the non- volatile memory 104, latency may be improved as compared to copying all the data in the memory image 802 regardless of whether the data has been modified.

FIG. 9 depicts a flowchart that illustrates an embodiment of a method 900 of performing a data save operation that copies data from a volatile memory to a non- volatile memory. The method 900 may be performed by a data storage device having a controller, a nonvolatile memory including a hibernate area, a volatile memory, a non- volatile memory interface, and a volatile memory interface. For example, the method 900 may be performed by the data storage device 102 of FIG. 1, FIG. 2, and FIG. 3. A determination is made, based on an indication from a host device, that the data storage device is to enter a low-power state, at 902. To illustrate, the controller 110 may receive one or more of the power event signals 220 from the host device 130. For example, the controller 110 may receive one or more hardware signals, such as the hardware signals 402 of FIG. 4, indicating the sleep state or the power off state.

Alternatively, the controller 110 may detect receipt of a hibernation instruction, such as the hibernation instruction 502 from the host device 130 of FIG. 5, indicating the hibernation state. Alternatively, the controller 110 may detect that a timer value exceeds a hibernation threshold, where the timer value indicates an elapsed time since receipt of a most recently received request from the host device to access the volatile memory. For example, a value of the volatile memory inactivity timer 604 of FIG. 6 may be determined to exceed the hibernation threshold 606.

In response to determining that the data storage device is to enter the low-power state, a data save operation that copies data from the volatile memory to the hibernate area of the non-volatile memory is performed by the controller, at 904. Copying the data to the non- volatile memory prevents loss of the data upon interruption of power to the volatile memory. For example, the data save operation may include bypassing the non- volatile memory interface 194 and the volatile memory interface 196 and copying the data 116 from the volatile memory 112 to the controller 110, and writing the data 116 from the controller 110 to the hibernate area 106 of the non- volatile memory 104 via the bus 250. Alternatively, the data save operation 114 may include bypassing the non- volatile memory interface 194 and the volatile memory interface 196 and generating the first bus control signal 314 to cause the hibernate data bus 312 to access the data 116 from the volatile memory 112 and generating the second bus control signal 316 to cause the hibernate data bus 312 to send the data 116 to the hibernate area 106 of the non- volatile memory 104. Upon completion of the data save operation, the volatile memory may be powered off by the controller while maintaining power to the controller, at 906. For example, the power control circuit 702 may detect that the data save operation 114 has completed. Upon detecting completion of the data save operation 114, the power control circuit 702 may cause the controller 110 to power off the volatile memory 112 while maintaining power to the controller 110.

Alternatively, upon completion of the data save operation, an indication may be sent to the host device that the data storage device is prepared for interruption of power supplied by the host device, at 908. For example, the indication 120 may be sent to the host device 130 that the data storage device 102 is prepared for interruption of power supplied by the host device 130. Alternatively, upon completion of the data save operation, a hibernation state may be entered, where entering the hibernation state is performed without host intervention or host action, at 910. For example, the data storage device 102 may enter the hibernation state automatically after the data save operation 114. In implementations where the volatile memory 112 is powered off but the controller 110 remains operational, powering off the volatile memory 112 reduces overall power consumption of the data storage device 102. Performing the data save operation 114 enables the data storage device 102, upon power up, to more quickly revert to a state that the data storage device 102 was in prior to entering the low-power state. The data 116 copied from the volatile memory 112 to the non- volatile memory 104 may be readily available to the host device 130 upon power up and without requiring participation of the host device in the data storage and the data retrieval related to the data save operation 114. In implementations where the host device 130 interrupts power to the data storage device 102, performing the data save operation 114 enables the data storage device to protect data stored at the volatile memory 112 prior to powering off and without requiring participation of the host device in the data storage and the data retrieval related to the data save operation 114.

FIG. 10 depicts a flowchart that illustrates another embodiment of a method 1000 of performing a data save operation that copies data from a volatile memory to a non- volatile memory. The method 1000 may be performed by a data storage device having a controller, a non-volatile memory, a volatile memory, a hibernate data bus that connects the non- volatile memory and the volatile memory, a non- volatile memory interface, and a volatile memory interface. For example, the method 1000 may be performed by the data storage device 102 of FIG. 1 and FIG. 3. A determination is made, based on an indication from a host device, that the data storage device is to enter a low-power state, at 1002. To illustrate, the controller 110 may receive one or more of the power event signals 220 from the host device 130. For example, the controller 110 may receive one or more hardware signals, such as the hardware signals 402 of FIG. 4, indicating the sleep state or the power off state.

In response to determining that the data storage device is to enter the low-power state, a data save operation that copies data from the volatile memory to the non- volatile memory is performed by the controller, at 1004. Copying the data to the non- volatile memory prevents loss of the data upon interruption of power to the volatile memory. For example, the data save operation may include bypassing the non- volatile memory interface 194 and the volatile memory interface 196 and copying the data 116 from the volatile memory 112 to the hibernate area 106 of the non- volatile memory 104 via the hibernate data bus 312 by generating the first bus control signal 314 to cause the hibernate data bus 312 to access the data 116 from the volatile memory 112 and generating the second bus control signal 316 to cause the hibernate data bus 312 to send the data 116 to the hibernate area 106 of the non- volatile memory 104.

Upon completion of the data save operation, the volatile memory may be powered off by the controller while maintaining power to the controller, at 1006. For example, the power control circuit 702 may detect that the data save operation 114 has completed. Upon detecting completion of the data save operation 114, the power control circuit 702 may cause the controller 110 to power off the volatile memory 112 while maintaining power to the controller 110.

Alternatively, upon completion of the data save operation, an indication may be sent to the host device that the data storage device is prepared for interruption of power supplied by the host device, at 1008. For example, the indication 120 may be sent to the host device 130 that the data storage device 102 is prepared for interruption of power supplied by the host device 130.

Alternatively, upon completion of the data save operation, a hibernation state may be entered, where entering the hibernation state is performed without host intervention or host action, at 1010. For example, the data storage device 102 may enter the hibernation state automatically after the data save operation 114. In implementations where the volatile memory 112 is powered off but the controller 110 remains operational, powering off the volatile memory 112 reduces overall power consumption of the data storage device 102. Performing the data save operation 114 enables the data storage device 102, upon power up, to more quickly revert to a state that the data storage device 102 was in prior to entering the low-power state. The data 116 copied from the volatile memory 112 to the non- volatile memory 104 may be readily available to the host device 130 upon power up and without requiring participation of the host device in the data storage and the data retrieval related to the data save operation 114. In implementations where the host device 130 interrupts power to the data storage device 102, performing the data save operation 114 enables the data storage device 102 to protect data stored at the volatile memory 112 prior to powering off and without requiring participation of the host device 130 in the data storage and the data retrieval related to the data save operation 114.

Although various components depicted herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable a data storage device, such as the data storage device 102 of FIG. 1, FIG. 2, and FIG. 3, to perform the particular functions attributed to such components, or any combination thereof. For example, the controller 110 of FIG. 1, FIG. 2, and FIG. 3 may represent physical components, such as controllers, processors, state machines, logic circuits, or other structures to cause the data save operation 114 to copy data from the volatile memory 112 to the non- volatile memory 104.

The controller 110 may be implemented using a microprocessor or microcontroller programmed to generate control information and to initiate and perform the data save operation 114. In a particular embodiment, the controller 110 includes a processor executing instructions that are stored at the non- volatile memory 104. Alternatively, or in addition, executable instructions that are executed by the processor may be stored at a separate memory location that is not part of the non- volatile memory 104, such as at a read-only memory (ROM). In a particular embodiment, the data storage device 102 may be a portable device configured to be selectively coupled to one or more external devices. For example, the data storage device 102 may be a removable device such as a universal serial bus (USB) flash drive or removable memory card. However, in other embodiments, the data storage device 102 may be attached or embedded within one or more host devices, such as within a housing of a portable communication device. For example, the data storage device 102 may be within a packaged apparatus, such as a wireless telephone, a personal digital assistant (PDA), a gaming device or console, a portable navigation device, a computer, or other device that uses internal non-volatile memory. In a particular embodiment, the data storage device 102 includes a non- volatile memory, such as a Flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), Divided bit-line NOR (DINOR), AND, high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other Flash memories), an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory

(EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), or any other type of memory.

The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

WHAT IS CLAIMED IS:

1. A method comprising:

in a data storage device with a controller, a non-volatile memory including a hibernate data area, and a volatile memory, wherein the data storage device includes a non- volatile memory interface to enable access to the non-volatile memory by a host device while the data storage device is operatively coupled to the host device and wherein the data storage device includes a volatile memory interface to enable access to the volatile memory by the host device while the data storage device is operatively coupled to the host device, performing, while the data storage device is operatively coupled to the host device:

determining, based on an indication from the host device, that the data storage device is to enter a low-power state; and

in response to determining that the data storage device is to enter the low-power state, performing, by the controller, a data save operation that bypasses the non- volatile memory interface and the volatile memory interface and that copies data from the volatile memory to the hibernate data area of the non-volatile memory.

2. The method of claim 1, wherein copying the data to the non- volatile memory prevents loss of the data upon interruption of power to the volatile memory.

3. The method of claim 1, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a power event signal from the host device, wherein the power event signal is a hardware signal indicating a sleep state or a power off state.

4. The method of claim 3, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation, wherein entering the hibernation state is performed without host intervention.

5. The method of claim 1, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a hibernation instruction from an application processor of the host device.

6. The method of claim 1, wherein the controller is configured to detect that a timer value exceeds a hibernation threshold, wherein the timer value indicates an elapsed time since receipt of a request from the host device to access the volatile memory.

7. The method of claim 6, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation.

8. The method of claim 7, wherein entering the hibernation state is performed without host action.

9. The method of claim 1, wherein the controller is further configured, upon completion of the data save operation, to power off the volatile memory while a power control circuit maintains power to the controller.

10. The method of claim 1, wherein the controller is further configured, upon completion of the data save operation, to provide an indication to the host device that the data storage device is prepared for interruption of power.

11. The method of claim 1 , wherein the controller is coupled to the non- volatile memory via a bus.

12. The method of claim 11, wherein the controller is configured to receive the data copied from the volatile memory and to write the data to the hibernate area of the nonvolatile memory via the bus.

13. The method of claim 11, wherein the data storage device further comprises a hibernate data bus that connects the non-volatile memory and the volatile memory, and wherein the controller is configured to generate a first bus control signal to cause the hibernate data bus to access the data from the volatile memory and to generate a second bus control signal to cause the hibernate data bus to send the data to the hibernate data area of the non-volatile memory.

14. The method of claim 1, wherein the controller is configured to perform a data restore operation that includes copying stored data from the non- volatile memory to the volatile memory to restore a memory image of the volatile memory, wherein the memory image includes a copy of data in at least a portion of the volatile memory.

15. The method of claim 1, wherein the controller is configured to perform the data storage operation by selectively copying portions of the volatile memory to the nonvolatile memory based on whether the portions have been modified since a most recent data restore operation.

16. A data storage device comprising:

a non-volatile memory including a hibernate data area;

a volatile memory;

a non-volatile memory interface to the non-volatile memory;

a volatile memory interface to the volatile memory; and

a controller, wherein the controller is configured, while the data storage device is operatively coupled to a host device, to perform a data save operation that bypasses the non- volatile memory interface and the volatile memory interface and that copies data from the volatile memory to the hibernate data area of the non- volatile memory in response to determining, based on an indication from the host device, that the data storage device is to enter a low-power state.

17. The data storage device of claim 16, wherein copying the data to the non- volatile memory prevents loss of the data upon interruption of power to the volatile memory.

18. The data storage device of claim 16, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a power event signal from the host device, wherein the power event signal is a hardware signal indicating a sleep state or a power off state.

19. The data storage device of claim 18, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation, wherein entering the hibernation state is performed without host intervention.

20. The data storage device of claim 16, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a hibernation instruction from an application processor of the host device.

21. The data storage device of claim 16, wherein the controller is configured to detect that a timer value exceeds a hibernation threshold, wherein the timer value indicates an elapsed time since receipt of a request from the host device to access the volatile memory.

22. The data storage device of claim 21, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation.

23. The data storage device of claim 22, wherein entering the hibernation state is performed without host action.

24. The data storage device of claim 16, wherein the controller is further configured, upon completion of the data save operation, to power off the volatile memory.

25. The data storage device of claim 16, wherein the controller is further configured, upon completion of the data save operation, to provide an indication to the host device that the data storage device is prepared for interruption of power.

26. The data storage device of claim 16, wherein the controller is coupled to the nonvolatile memory via a bus.

27. The data storage device of claim 26, wherein the controller is configured to receive the data copied from the volatile memory and to write the data to the hibernate data area of the non- volatile memory via the bus.

28. The data storage device of claim 26, further comprising a hibernate data bus that connects the non- volatile memory and the volatile memory, and wherein the controller is configured to generate a first bus control signal to cause the hibernate data bus to access the data from the volatile memory and to generate a second bus control signal to cause the hibernate data bus to send the data to the hibernate data area of the non- volatile memory.

29. The data storage device of claim 16, wherein the controller is configured to perform a data restore operation that includes copying stored data from the non- volatile memory to the volatile memory to restore a memory image of the volatile memory, wherein the memory image includes a copy of data in at least a portion of the volatile memory.

30. The data storage device of claim 16, wherein the controller is configured to perform the data storage operation by selectively copying portions of the volatile memory to the non- volatile memory based on whether the portions have been modified since a most recent data restore operation.

31. A method comprising:

in a data storage device with a controller, a non- volatile memory, a volatile memory, and a hibernate data bus, wherein the data storage device includes a non-volatile memory interface to enable access to the non-volatile memory by a host device while the data storage device is operatively coupled to the host device and wherein the data storage device includes a volatile memory interface to enable access to the volatile memory by the host device while the data storage device is operatively coupled to the host device, performing, while the data storage device is operatively coupled to the host device:

in response to determining that the data storage device is to enter the low-power state, performing, by the controller, a data save operation that bypasses the non- volatile memory interface and the volatile memory interface and that copies data from the volatile memory to the non- volatile memory via the hibernate data bus.

32. The method of claim 31, further comprising entering a hibernation state after performing the data save operation.

33. The method of claim 31, further comprising, upon completion of the data save operation, powering off the volatile memory while maintaining power to the controller.

34. The method of claim 31, further comprising, upon completion of the data save operation, sending an indication to the host device that the data storage device is prepared for interruption of power.

35. The method of claim 31 , wherein the non- volatile memory includes a hibernate area, wherein the controller is coupled to the hibernate data bus, wherein the hibernate data bus connects the non- volatile memory and the volatile memory, and wherein performing the data save operation includes:

generating a first bus control signal to cause the hibernate data bus to access the data from the volatile memory; and

generating a second bus control signal to cause the hibernate data bus to send the data to the hibernate area of the non-volatile memory.

36. A data storage device comprising:

a non- volatile memory;

a volatile memory;

a hibernate data bus that connects the non-volatile memory and the volatile memory; a non-volatile memory interface to the non-volatile memory;

a volatile memory interface to the volatile memory; and

a controller, wherein the controller is configured, while the data storage device is operatively coupled to a host device, to perform a data save operation that bypasses the non- volatile memory interface and the volatile memory interface and that copies data from the volatile memory to the non- volatile memory via the hibernate data bus in response to determining, based on an indication from the host device, that the data storage device is to enter a low-power state.

37. The data storage device of claim 36, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a power event signal from the host device, wherein the power event signal is a hardware signal indicating a sleep state or a power off state.

38. The data storage device of claim 36, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a hibernation instruction from an application processor of the host device.

39. The data storage device of claim 36, wherein the controller is configured to detect that a timer value exceeds a hibernation threshold, wherein the timer value indicates an elapsed time since receipt of a request from the host device to access the volatile memory.