WO2016076850A1

WO2016076850A1 - Data write back

Info

Publication number: WO2016076850A1
Application number: PCT/US2014/065193
Authority: WO
Inventors: Patrick A. Raymond; Nathan S. DENEUI; Dennis W. FOTHERGILL
Original assignee: Hewlett Packard Enterprise Development Lp
Priority date: 2014-11-12
Filing date: 2014-11-12
Publication date: 2016-05-19
Also published as: TW201633050A

Abstract

Example implementations relate to data write back. For example, a data write back system, comprising a micro-uninterruptible power supply (µUPS) module to signal a primary power supply interruption to a controller, and the controller to segregate a portion of memory, and restore data to the segregated portion of memory in response to the primary power supply interruption signal.

Description

DATA WRITE BACK

Background

[0001] As reliance on computing systems continues to grow, so too does the demand for reliable power systems and back-up schemes for these computing systems. Servers, for example, may provide architectures for backing up data to flash or persistent memory as well as back-up power sources for powering this back-up of data after the loss of power.

Brief Description of the Drawings

[0001] Figure 1 illustrates a block diagram of an example of a system for data write back according to the present disclosure;

[0002] Figure 2 illustrates a block diagram of an example of a system for data write back according to the present disclosure;

[0003] Figure 3 illustrates a block diagram of an example of a system for data write back, according to the present disclosure; and

[0004] Figure 4 illustrates an example data write back flow method according to the present disclosure. Detailed Description

[0005] A computing data storage system can include a number of nodes that support a number of loads. The nodes can be a number of servers, for example. A number of loads can include storage controllers or devices associated with the servers. For example, a load can include cache memory, dual inline memory modules (DIMMs), Non-Volatile Dual In-Line Memory Modules (NVDIMMs), and/or array control logic, among other storage controllers and/or devices associated with the servers.

[0006] A removal of a primary power supply can be scheduled or un-scheduled. For instance, a scheduled removal of the primary power supply can be the result of scheduled maintenance on the number of nodes and/or the number of loads. An unscheduled primary power supply removal can be an interruption in the primary power supply. An un-scheduled primary power supply removal can occur when, for example, the primary power supply fails momentarily and/or for an extended period of time.

Failure can include an unintentional loss of power to nodes and/or loads from the primary power supply.

[0007] A micro-uninterruptible power supply ( U PS) can be a secondary power supply that is used to provide emergency power to a load when a primary power supply (e.g., input power source) is interrupted. Interruption of a primary power supply can refer to a power failure, power surge, inadequate power, and/or transient faults. AiUPS can provide near-instantaneous protection from power interruptions by supplying energy stored in batteries, supercapacitors, or flywheels, among others.

[0008] It may be desirable to move data from cache memory in the number of nodes to non-volatile memory upon the removal of a primary power supply. However, moving data from cache memory to non-volatile memory can involve a secondary power supply. A μΙΙΡβ can be a secondary power supply that is used to provide power for moving data from cache memory to non-volatile memory when the primary power is removed (e.g., backup mode). Further, the μΙΙΡβ can reside in a power supply slot and/or be a shared μΙΙΡβ, in that the shared μΙΙΡβ associated with a particular node is shared among a plurality of loads associated with that node.

[0009] Examples of the present disclosure can include a system that includes a [iUPS to signal a primary power supply interruption to a controller. The controller can segregate a portion of memory and/or restore data to a segregated portion of memory in response to the primary power supply interruption signal.

[0010] Figure 1 illustrates a block diagram of an example of a system 100 for data write back according to the present disclosure. As illustrated in Figure 1 , the system 100 can include a μΙΙΡβ 102 to signal 122 a primary power supply interruption to a controller 104. A μΙΙΡβ can refer to an electrical apparatus that provides a temporary source of power to a load 1 18 when a primary power supply is interrupted (e.g., fails) and can be integrated into a node 1 16 (e.g., an integrated component of the server node). An integrated component of the node 1 16, as used herein, can include a separate component from the node 1 16 that is combined with the node 1 16 such that the node 1 16 and the integrated component function together as a single unit. For example, a μΙΙΡβ can reside in a power supply slot of the node 1 16 (e.g., be physically and/or directly plugged in to a power supply slot of the node 1 16). The μΙΙΡβ 102 can be used to protect hardware and components of the system 100, such as a system central processing unit (CPU) 106 and system DIMMs 108, from data loss in response to the primary power supply interruption.

[0011] The controller 104 can manage access to memory 1 10, 1 12, and the controller 104 can segregate a portion of memory 1 14. The segregated portion of memory can be performed by the controller 104 at power up. The controller can segregate a portion of memory 1 14, for data storage. In some examples, the

segregated portion of memory 1 14 is within a hidden partition. A hidden partition, as used herein, can refer to a segment of non-volatile memory that is not visible to the CPU, and is exclusively reserved for a data dump upon a primary power supply interruption. A data dump can refer to an amount of data transferred from one system or location to another. The controller can create a hidden partition in which the segregated portion of memory 1 14 can reside in preparation for a data dump.

[0012] In some examples, the controller 104 can identify within the portion of segregated memory an associated number of drives within the system 100. The controller 104 can identify a sequential bandwidth of the associated number of the drives. In some examples, the controller 104 can include a delay period to assign, for restoration, a portion of persistent data to the associated number of drives. For example, the controller can delay assigning the data to be restored. Further, the controller 104 can restore data to the segregated portion of memory 1 14 in response to the primary power supply interruption signal 122.

[0013] In some examples, the μΙΙΡβ 102 can be an integrated component of a node 1 16 and/or provide the temporary source of power to a load 1 18 associated with a node 1 16 for a threshold of time. For example, the integrated power supply can include a iUPS that is used to provide power for moving data from cache memory to nonvolatile memory when the primary power is interrupted. Further, the μΙΙΡβ can reside in a power supply slot of the node and/or be a shared μΙΙΡβ, in that the shared μΙΙΡβ associated with a particular node is shared among a plurality of loads associated with that node. The μΙΙΡβ can be integrated into the node. The node 1 16 and the load 1 18 can be in communication via pathway 120 (e.g., link). While a single load 1 18 is illustrated in Figure 1 , more than one load may be hosted by node 1 16. For instance, the node 1 16 can host a number of devices, such as local memory or data storage (e.g., referred generally as memory). The memory may contain volatile and non-volatile memory (e.g., cache, DIMM, NVDIMM). Node 1 16 can include other devices such as cache memory, DIMMs, array control logic, and storage controllers, among other devices associated with the node 1 16. In some examples, the node 1 16 can also include a control logic unit (not shown).

[0014] In some examples, the segregated portion of memory 1 14 can be available for data write back during a primary power supply interruption. That is, upon primary power supply interruption, data can be dumped into the segregated portion of memory 1 14 and data write back to non-volatile memory can be performed. In some examples, the controller 104 can linearly restore the data from the data dump. As used herein, a linear restoration of data can refer to a straight chain of data. That is, the data is saved and restored in a sequential order. Further, the controller 104 can, in some examples, restore system functions associated with the data. In other words, data saved with the segregated portion of memory 1 14 can be implemented and restored to the functionality of the system 100.

[0015] A primary power supply interruption signal can be a signal that

communicates an instruction and/or a command such as an instruction and/or command to initiate a sequenced shutdown of the node 1 16 including writing data from a volatile memory location of the node 1 16 to a non-volatile memory location of the node 1 16. In an example, a primary power supply interruption signal can include a signal from the controller 104 communicated through a system complex programmable logic device (CPLD) wired into a power button logic of the node 1 16 to initiate a sequenced shutdown of the node 1 16 as if a power button on the node 1 16 had been pressed.

[0016] In an additional example, a primary power supply interruption signal can be a signal from a primary power supply unit of the primary power supply propagated using a general purpose interface (GPI) pin on a southbridge (e.g., one of two chips in a core logic chipset on a motherboard, in a northbridge/southbridge chipset architecture, of a CPU) of a CPU of the node 1 16. In such an additional example, the pin can be programmed to signal a primary power supply interruption to the operating system and the node 1 16 can then execute a segregate engine, as further discussed in Figure 2.

[0017] Figure 2 illustrates a block diagram of an example of a system 230 for data write back according to the present disclosure. The system 230 can utilize hardware, software (e.g., program instructions), firmware, and/or logic to perform a number of functions described herein. The system 230 can be any combination of hardware and program instructions configured to share information. The hardware can, for example, include a processing resource 232 and a memory resource 236 (e.g., computer or machine readable medium (CRM/MRM), database, etc.). A processing resource 232, as used herein, can include one or more processors capable of executing instructions stored by the memory resource 236. The processing resource 232 may be implemented in a single node (e.g., node 1 16 illustrated in Figure 1 ) or distributed across multiple nodes. The program instructions (e.g., computer or machine readable instructions (CRI/MRI)) can include instructions stored on the memory resource 236 and executable by the processing resource 232 to perform a particular function, task and/or action (e.g., segregate a portion of memory 238).

[0018] The memory resource 236 can be a non-transitory MRM, include one or more memory components capable of storing instructions that can be executed by a processing resource 232, and may be integrated in a single node or distributed across multiple nodes. The memory resource 236 can be in communication with the processing resource 232 via a communication link (e.g., a path) 234. The

communication link 234 can provide a wired and/or wireless connection between the processing resource 232 and the memory resource 236.

[0019] As illustrated in Figure 2, the memory resource 236 can include segregate 238 instructions, signal 240 instructions, and/or restore data to segregate instructions. As used herein, instructions include at least software that can be executed by a processing resource, for example, processing resource 232, to perform a particular task, function and/or action. The plurality of instructions may be combined or may be subroutines of other instructions. As shown in Figure 2, the segregate 238 instructions, signal 240 instructions, and/or restore 242 instructions can be individual instructions located on one memory resource 236. Examples are not so limited, however, and a plurality of instructions can be located at separate and distinct memory resource locations, for example, in a distributed computing environment, cloud computing environment, etc.

[0020] For example, the system 230 can include instructions executable to identify, using a controller (e.g., controller 104 illustrated in Figure 1 ), the hidden partition, including the segregated portion of memory. That is, the controller can identify the hidden partition and locate the segregated portion of memory during a data dump. In other words, the controller can, in some instances, guide the data to the segregated portion of memory for cache write back. The data within the segregated portion of memory can be restored and implemented within the system.

[0021] Each of the plurality of instructions can include instructions that when executed by the processing resource 232 can function as an engine. For example, segregate 238 instructions can include instructions that when executed by the processing resource 232 can function as a segregation engine (not shown). The signal 240 instructions can include instructions that when executed by the processing resource 232 can function as a signal engine (not shown). The restore 242 instructions can include instructions that when executed by the processing resource 232 can function as a restore engine (not shown). [0022] The plurality of engines (not shown) can include a combination of hardware and software (e.g., program instructions), but at least include hardware configured to perform particular functions, tasks, and/or actions. For example, the plurality of engines can be used to segregate, using a controller coupled to a node, a portion of memory, wherein the segregated portion of memory is a hidden partition, signal, using a μΙΙΡβ to the controller, a primary power supply interruption, wherein theiUPS is integrated to the node, and restore, in response to the signaled primary power supply interruption, data to the segregated portion of memory.

[0023] The system 230 can include a database (not shown) accessible to and in communication with the plurality of engines (e.g., segregation engine, signal engine, restore engine). The system 230 can include additional or fewer engines than described to perform the various functions described herein and examples are not limited to the example shown in Figure 2. The system 230 can include hardware, for example, in the form of transistor logic and/or application specific integrated circuitry (ASICs), firmware, and software, for example, in the form of machine readable and executable instructions (e.g., program instructions stored in a machine readable medium), which, in cooperation can form the computing device as discussed in connection with Figure 2.

[0024] Examples are not limited to the example instructions shown in Figure 2 and in some cases a number of instructions can operate together to function as a particular engine. In addition, one or more engines described, or one or more instructions described may be combined or may be a sub-engine of another engine. Further, the engines and/or instructions of Figure 2 can be located in a single system and/or computing system or reside in separate distinct locations in a distributed network, cloud computing, enterprise service environment (e.g., Software as a Service (SaaS) environment), etc.

[0025] Figure 3 illustrates a block diagram of an example of a segregated portion of memory 314 for data write back, according to the present disclosure. The

segregated portion of memory 314 can include within a segregated portion of memory (e.g., portion 1 14 illustrated in Figure 1 ) cache information 352, metadata 354, and data 356. [0026] In some examples, the segregation of a portion of memory can be initiated during system power up. That is, in some instances, the portion of memory (e.g., portion 1 14 as illustrated in Figure 1 ) can be segregated prior to a primary power supply interruption. The portion of memory can be segregated by a controller as a precaution in the event of a primary power supply interruption and forthcoming data dump.

[0027] In some examples, a controller (e.g., controller 104 illustrated in Figure 1 ) can sequentially transfer data to the segregated portion of memory. As illustrated in Figure 3, the data can be sequentially ordered such that the different types of data (e.g., cache data 352, metadata 354, and data 356) are categorized.

[0028] In some examples, restoring data to the segregated portion of memory can restore functions associated with the data upon system power up. That is, the data dump into the segregated portion of memory can save the data and implement the data, thereby restoring the functions associated with the saved data. For example, cache data 352 stored within the segregated portion of memory can be used by the CPU upon system power up. For instance, the cache data can be written back such that the CPU can utilize the data.

[0029] Figure 4 illustrates an example data write back flow method 460 according to the present disclosure. At 462, the method 460 can include segregating, using a controller coupled to a node, a portion of memory, wherein the segregated portion of memory is a hidden partition. Upon power up, the controller can segregate a portion of memory to be designated for memory in the event of a primary power interruption. The segregated portion of memory can be a hidden partition. The hidden partition can isolate the portion of memory such that the computing system does not use the portion of memory for memory storage during normal functioning of the system.

[0030] At 464, the method 460 can include signaling, using a μυΡβ, to the controller a primary power supply interruption. In some examples, the iUPS can be integrated to the node and can include providing backup power supply as a temporary source of power to the node for a threshold of time. That is, the [iUPS can be associated with the node and provide a source of backup power supply upon primary power supply interruption. The μυΡβ can provide the backup power supply for a finite period of time. For example, upon primary power supply interruption, the μΙΙΡβ can provide power to the node for a threshold of time, such as sixty (60) seconds.

[0031] At 466, the method 460 can include identifying, using the controller and in response to the signal, the hidden partition including the segregated portion of memory. As discussed in relation to 464, the μΙΙΡβ can provide power for a threshold of time, during which time the controller can identify the hidden partition. Once the hidden partition is identified, the controller can proceed to data dump. That is, the controller can transfer data to the hidden partition, including the segregated portion of memory. The data can be saved within the segregated portion of memory and written to nonvolatile memory. In some examples, the method 460 can include sequentially transferring data to the segregated portion of memory. For instance, the controller can transfer the data in a sequential manner.

[0032] At 468, the method 460 can include restoring, in response to the identified segregated portion of memory, data to the segregated portion of memory. For example, the data saved within the segregated portion of memory can be written to non-volatile memory. The data can be implemented and restored upon system power up. That is, the data dump to the segregated portion of memory can be saved, implemented, and thereby restored to the system.

[0033] In some examples, the method 460 can include a plurality of controllers, including the aforementioned controller and a plurality of drives associated with a plurality of portions of memory, performing a plurality of restorations of data to a plurality of segregated portions of memory. That is, multiple controllers running multiple sets of drives can perform data dumps and restore data to memory.

[0034] In the foregoing detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure, and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. [0035] The figures herein follow a numbering convention in which the first digit corresponds to the drawing figure number and the remaining digits identify an element or component in the drawing. Elements shown in the various figures herein can be added, exchanged, and/or eliminated so as to provide a number of additional examples of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the examples of the present disclosure, and should not be taken in a limiting sense. Further, as used herein, "a number of" an element and/or feature can refer to one or more of such elements and/or features.

[0036] As used herein, "logic" is an alternative or additional processing resource to perform a particular action and/or function, etc., described herein, which includes hardware, e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc., as opposed to computer executable instructions (e.g., software firmware, etc.) stored in memory and executable by a processor.

Claims

What is claimed:

1 . A data write back system, comprising:

a micro-uninterruptible power supply ( U PS) to signal a primary power supply interruption to a controller; and

the controller to:

segregate a portion of memory; and

restore data to the segregated portion of memory in response to the primary power supply interruption signal.

2. The system of claim 1 , the controller to identify within the segregated portion of memory:

an associated number of drives within the system;

a sequential bandwidth of the associated number of drives; and

a delay period to assign, for restoration, a portion of persistent data to the associated number of drives.

3. The system of claim 1 , wherein the μΙΙΡβ is an integrated component of a node and provides a temporary source of power to a load associated with the node for a threshold of time.

4. The system of claim 1 , wherein the segregated portion of memory is within a hidden partition.

5. The system of claim 1 , comprising the controller to:

linearly restore the data; and

restore system functions associated with the data.

6. The system of claim 1 , wherein the segregated portion of memory is available for data write back during a power supply interruption.

7. A non-transitory machine readable medium storing instructions executable by a processing resource to cause a computer to:

segregate, using a controller coupled to a node, a portion of memory, wherein the segregated portion of memory is a hidden partition;

signal to the controller, using a micro-uninterruptible power supply (μΙΙΡβ), a primary power supply interruption,

wherein the μΙΙΡβ is integrated to the node; and

restore, in response to the signaled primary power supply interruption, data to the segregated portion of memory.

8. The medium of claim 7, further comprising instructions executable to identify, using the controller, the hidden partition including the segregated portion of memory.

9. The medium of claim 7, further comprising instructions executable to sequentially transfer data to the segregated memory.

10. The medium of claim 7, wherein the instructions executable to restore data to the segregated portion of memory include instructions executable to restore functions associated with the data upon power up.

1 1. The medium of claim 7, wherein the instructions executable to segregate a portion of memory are initiated during system power up.

12. A method of data write back, comprising:

segregating, using a controller coupled to a node, a portion of memory, wherein the segregated portion of memory is a hidden partition;

signaling to the controller, using a micro-uninterruptible power supply (μΙΙΡβ), a primary power supply interruption;

identifying, using the controller and in response to the signal, the hidden partition including the segregated portion of memory; and restoring, in response to the identified segregated portion of memory, data to the segregated portion of memory.

13. The method of claim 12, further comprising sequentially transferring data to the segregated portion of memory.

14. The method of claim 12, further comprising performing a plurality of data restorations to a plurality of segregated portions of memory using a plurality of controllers and a plurality of drives associated with a plurality of segregated portions of memory.

15. The method of claim 12, wherein the μΙΙΡβ is integrated into the node and provides backup power supply as a temporary source of power to the node for a threshold of time.