WO2017054487A1 - Power-down protection method and apparatus, and electronic device - Google Patents

Power-down protection method and apparatus, and electronic device Download PDF

Info

Publication number
WO2017054487A1
WO2017054487A1 PCT/CN2016/084168 CN2016084168W WO2017054487A1 WO 2017054487 A1 WO2017054487 A1 WO 2017054487A1 CN 2016084168 W CN2016084168 W CN 2016084168W WO 2017054487 A1 WO2017054487 A1 WO 2017054487A1
Authority
WO
WIPO (PCT)
Prior art keywords
power
fpga
data
indication signal
electronic device
Prior art date
Application number
PCT/CN2016/084168
Other languages
French (fr)
Chinese (zh)
Inventor
周斌
刘磊山
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2017054487A1 publication Critical patent/WO2017054487A1/en

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16Protection against loss of memory contents
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to, but is not limited to, an electronic device power-down technology, and more particularly to a method, device, and electronic device for power-down protection.
  • power-down protection is to use a mechanism to ensure the certainty of the operating state of the system and the integrity of the recorded data when the system loses power. When the system resumes power supply, it can restore the system's field data in time to avoid system generation. confusion.
  • the related technology that uses the pure software mode for power-down protection has the following problems: When a power failure is detected, an interrupt is triggered, and the running data is written into the non-volatile memory.
  • the software system is more complicated, especially the operating system is introduced, the data is operated by means of file reading and writing.
  • the data volume is generally large, and the data protection operation takes a long time.
  • the power supply requirement is high, and the storage capacitor is obviously No longer suitable, so power-down protection based on software-only is no longer reliable.
  • the technical problem to be solved by the embodiments of the present invention is to provide a method, a device, and an electronic device for power-down protection, which are used to solve the defects in the related art that the power-down protection based on the pure software mode is no longer reliable.
  • a method for power-down protection is applied to an electronic device, the electronic device comprising a field programmable gate array unit FPGA, the method comprising: monitoring an electrical signal output by the power source; and detecting that the fluctuation of the electrical signal is within a threshold range When outputting the first indication signal as the power down indication signal, when And detecting, when the fluctuation of the electrical signal exceeds the threshold range, outputting a second indication signal as a power down indication signal; when monitoring the outputting the second indication signal, synchronizing data with the processor unit and the current system The time is written to the non-volatile flash memory and the stored data synchronized with the processor unit is loaded after the electronic device is powered up next time.
  • the electrical signal is a voltage
  • the first indication signal is a high level
  • the second indication signal is a low level
  • the second indication signal includes: outputting a high level when the fluctuation of the voltage is detected within the threshold range, and outputting a low level when detecting that the fluctuation of the voltage exceeds a threshold range.
  • the fluctuation of the electrical signal exceeding the threshold range includes that the electrical signal output by the power supply fluctuates downward beyond a lower threshold of the threshold range.
  • writing data synchronized with the processor unit and current system time to the non-volatile flash memory includes:
  • the state data, the operation data and the memory data generated by the system software and required to be protected by the processor unit are written into the FPGA internal register or the internal random access memory; and the current system time is written by the processor unit into the FPGA internal register, the FPGA Start the internal system timing, wait for the power supply to be powered down; after the power supply is powered off, the FPGA supplies power to the FPGA by the storage capacitor.
  • the FPGA writes the status data, operation data, memory data, and system time when the system is powered down. Into the non-volatile flash memory built into the FPGA.
  • the method further includes: when detecting the outputting the second indication signal, if the power supply is not actually powered down, and the software of the electronic device is not affected, the processor unit controls the FPGA to erase the non-easy The corresponding address in the flash memory, again waiting for the power to be powered down.
  • the loading the stored data synchronized with the processor unit after the next power-on of the electronic device comprises: after the electronic device is started, the FPGA saves the non-volatile after the last power-down
  • the protected data in the flash memory is read into the FPGA internal register or the internal random access memory, and the processor unit reads the internal register of the FPGA or the internal random access memory through the data read channel to recover the data;
  • the FPGA erases the address space corresponding to the data in the flash.
  • a device for power failure protection applied to an electronic device, comprising: a voltage monitoring unit, a field programmable gate array unit FPGA and a processor unit;
  • a voltage monitoring unit configured to monitor an electrical signal output by the power source, and when detecting that the fluctuation of the electrical signal is within a threshold range, outputting a first indication signal as a power failure indication signal, when the fluctuation of the electrical signal is detected to exceed In the threshold range, a second indication signal is output as a power down indication signal.
  • the FPGA is configured to, when detecting the outputting the second indication signal, write data synchronized with the processor unit and current system time to the non-volatile flash memory, and load the storage after the electronic device is powered on next time The data synchronized with the processor unit.
  • the electrical signal is a voltage
  • the first indication signal is a high level
  • the second indication signal is a low level
  • the voltage monitoring unit includes: a power down indication module, configured to monitor the When the fluctuation of the voltage is within the threshold range, a high level is output, and when the voltage fluctuation is detected to exceed the threshold range, a low level is output.
  • the fluctuation of the electrical signal exceeding the threshold range includes: the electrical signal output by the power source fluctuates downward beyond a lower threshold of the threshold range.
  • the device further includes: a storage capacitor.
  • the processor unit is configured to write the protected data generated when the system software is running into the FPGA internal register or the internal random access memory; and, write the current system time into the FPGA internal register, and the FPGA starts the internal system timing, waiting for the power supply to be powered down.
  • the storage capacitor is set to supply power to the FPGA after the power supply is powered off; the FPGA is also configured to write the state data, the operation data, the memory data, and the system time when the power is off after the system is powered down. Flash Flash.
  • the processor unit is configured to control the FPGA to erase non-volatile if the power is not actually powered down and the operation of the software of the electronic device is not affected when the second indication signal is detected to be output. The corresponding address in the flash memory, again waiting for the power to be powered down.
  • the FPGA is further configured to: after the electronic device is started, the FPGA reads the protected data saved in the non-volatile flash memory after the last power-down into the FPGA internal register or the internal random access memory;
  • the processor unit is also configured to read the interior of the FPGA through the data read channel a register or an internal random access memory to recover the data;
  • the FPGA is further configured to erase the address space corresponding to the data in the Flash after the data is read through the data read channel.
  • An electronic device comprising the above-described device for power-down protection.
  • a computer readable storage medium storing computer executable instructions that, when executed by a processor, implement the power down protection method.
  • the beneficial effects of the solution of the embodiment of the present invention are as follows: the data storage is performed outside the processor unit after the power is turned off, the operation of the processor unit and the operating system after the power failure is reduced, and the pure software protection method is faster, and the power supply accident can be ensured. Data is safely recorded in a power-down environment, conserving power and enabling instant storage of data.
  • FIG. 1 is a schematic flow chart of a method for power failure protection according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a working process of an electronic device before powering down and after power-off according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a workflow after an electronic device is powered on according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a device and an electronic device for power failure protection according to an embodiment of the present invention
  • FIG. 5 is a structural block diagram of a device for power failure protection according to an embodiment of the present invention.
  • An embodiment of the present invention provides a method for power-down protection, which is applied to an electronic device.
  • the electronic device includes a Field-Programmable Gate Array (FPGA), and the method includes steps S101-S102. :
  • S101 Monitor an electrical signal output by the power source, and when detecting that the fluctuation of the electrical signal is within a threshold range, output a first indication signal as a power-down indication signal, when the fluctuation of the monitored electrical signal exceeds the threshold range, A second indication signal is output as a power down indication signal.
  • the technical solution provided by the application after the power is turned off, the data is stored outside the CPU, and the data is pre-backup in the internal register of the FPGA or the internal random access memory.
  • the FPGA directly writes the data into the built-in FLash, and implements the data more quickly than the pure software method. Storage; no CPU and operating system intervention is required. After power failure, the storage capacitor only needs to supply power to the FPGA, save power, and have low capacitance requirements. It can ensure that important data is safely recorded in the environment of unexpected power failure. And the implementation cost is low.
  • Software refers to the system software that the CPU runs, generally referring to the operating system (OS).
  • the storage subsystem (non-volatile Flash) of the FPGA and FPGA is used to store and return protected data.
  • the FPGA uses XILINX's Spartan-3AN series FPGA, which has its own internal registers or internal random access memory, as well as non-volatile Flash.
  • the non-volatile flash has a storage space of 11Mb and has enough space to store protected data.
  • the use of this built-in Flash FPGA not only saves cost, reduces PCB layout area, but also reduces power consumption compared to using two discrete devices, which is especially important for power supply after power-down.
  • the internal Flash of the FPGA acts as a non-volatile memory that can erase and reprogram the address space of a minimum of one page (256 Bytes). An erase operation is required before the memory space is programmed, and the erase operation takes a long time relative to the write operation. Taking the Flash built in the Spartan-3AN series FPGA as an example, writing a page takes 4 to 6 milliseconds, and erasing a page takes about 32 to 35 milliseconds.
  • the pre-erase is implemented by the CPU controlling the FPGA in a pre-erase manner to ensure that the FPGA only needs to perform a write operation after the power is turned off. When the fluctuation of the power supply voltage exceeds the threshold, the power-down indication signal received by the FPGA is low, and the Flash write operation is started.
  • the electrical signal is a voltage; the first indication signal is a high level; and the second indication signal is a low level;
  • the second indication signal includes: outputting a high level when the fluctuation of the voltage is detected within the threshold range, and outputting a low level when detecting that the fluctuation of the voltage exceeds a threshold range.
  • the voltage is used as the electrical signal.
  • the power-down indication signal When the voltage fluctuation is within the threshold range, the power-down indication signal outputs a high level as the first indication signal. When the voltage fluctuation exceeds the threshold range, the power-down indication signal outputs a low level as the first Two indication signals.
  • the threshold range has an upper threshold and a lower threshold.
  • the fluctuation of the electrical signal exceeding the threshold range specifically refers to the lower threshold of the electrical signal fluctuating downward beyond the threshold range.
  • the FPGA writes the protected data and its internal system time written to its internal registers or internal random access memory through the data backup channel to the non-volatile flash memory (Flash).
  • writing data synchronized with the processor unit and current system time to the non-volatile flash memory includes:
  • the protected data generated by the system software when the system software is running is written into the FPGA internal register or the internal random access memory by the processor unit; and, by the processor unit, the current system time is written into the FPGA internal register, and the FPGA starts the internal system timing, waiting for the power supply to occur. Power down.
  • the FPGA After the power supply is powered off, the FPGA is powered by the storage capacitor.
  • the FPGA writes the status data, operation data, memory data, and system time during power-down to the non-volatile flash memory after the system is powered down.
  • the status data, the operation data, and the memory data are all the protected data.
  • the FPGA is powered by the storage capacitor during the data write of the FPGA.
  • the FPGA captures the power-down indication signal to a low level, and writes the protected data through the data backup channel to its internal register or internal random access memory. Write to Flash along with the internal system time.
  • the method further includes: when monitoring the outputting the second indication signal, if the power supply is not actually powered down, and the operation of the software of the electronic device is not affected, the processor unit controls the FPGA to erase the Flash. The corresponding address in the middle, wait for the power supply to power down again.
  • the power-down indication signal is low, but the actual power supply is not powered down, and the operating system of the electronic device is still running normally, then the CPU controls the FPGA to erase the corresponding address in the Flash, and waits for the power supply to be powered down again.
  • loading the stored data synchronized with the processor unit after the next power-on of the electronic device includes:
  • the FPGA reads the state data, the operation data, and the memory data stored in the Flash after the last power-down, and reads the FPGA into the internal register or the internal random memory, and the processor unit reads the FPGA through the data read channel.
  • Internal register or internal random access memory recovery The data;
  • the FPGA erases the address space corresponding to the data of the flash.
  • the embodiment of the invention provides an implementation method for implementing power-down protection data based on an FPGA built in Flash, which can write the current system time and protected data in the power failure to the FPGA within tens of milliseconds after the power is turned off.
  • the built-in Flash when the electronic device is powered on again, the FPGA reads the data in the Flash, and then the CPU reads back the FPGA data, so that the important data is safely saved when the power is turned off.
  • the working process of the electronic device before power failure and when power failure occurs includes steps S201-S206:
  • step 201 the fluctuation generated by the electrical signal output by the power source is monitored, and generally the voltage is used as the electrical signal.
  • Step 202 Determine whether the fluctuation of the voltage exceeds the threshold range. When the fluctuation of the voltage exceeds the threshold, the process proceeds to step 203, and when the fluctuation of the voltage does not exceed the threshold, the process proceeds to step 201.
  • Step 203 The FPGA receives the power-down indication signal to be low, indicating that the voltage fluctuation exceeds the threshold, and the data synchronized with the processor unit CPU and the current time are written into the Flash.
  • step 204 it is determined whether the power source is actually powered down. If it is determined that the power source is indeed powered down, then step 206 is performed. If it is determined that the power source is not actually powered down, then step 205 is performed.
  • Step 205 the power supply fluctuation exceeds the threshold, but in fact, the power supply may not be powered down, and the system software does not stop working; to prevent such misoperation, the CPU controls the FPGA to erase the built-in Flash again;
  • step 206 the power system is powered off, and the power-on workflow of the electronic device system is executed when the power is turned on again.
  • the workflow after the electronic device is powered on includes steps S301-S307:
  • Step 301 the electronic device is powered on, and the protected data in the built-in flash is read into an internal register of the FPGA or an internal random access memory after the FPGA is ready.
  • Step 302 The processor unit CPU reads an internal register of the FPGA or an internal random access memory through the data read channel, and acquires the protected data saved when the power is last powered off.
  • Step 303 the CPU finishes reading the protected data, and controls the FPGA to erase the flash address. Regional data.
  • the next step is to prepare the electronic device for the next possible power failure event under normal working conditions.
  • Step 304 in order to ensure the real-time and accuracy of the protected data, in the normal working state, the current unit time is written into the FPGA by the processor unit, the FPGA starts the internal timing, and the high-precision crystal oscillator is used to ensure the internal system time and reality of the FPGA. System time keeps small errors.
  • the power-down time is written to the flash together with the protected data: the power supply is powered down, causing the processor unit to stop working momentarily, the external system time is lost, and the FPGA writes the internal system time to Flash.
  • step 305 the FPGA starts to start timing after receiving the system time sent by the CPU, and uses precise timing to ensure synchronization with the system time.
  • Step 306 the CPU writes the data to be protected to the FPGA internal register or the internal random access memory through the data backup channel during operation to ensure that important data is backed up in real time in the FPGA, including:
  • the processor unit writes state data, operation data and memory data generated by the system software and needs to be protected into the FPGA internal register or the internal random access memory; and the processor unit writes the current system time to the FPGA internal register, and the FPGA starts the internal The system clocks and waits for the power to be powered down. After the power supply is powered off, the FPGA is powered by the storage capacitor. The FPGA writes the status data, operation data, memory data, and system time during power-down to the non-volatile flash memory after the system is powered down.
  • step 307 the electronic device is ready to wait for the power to be powered down again.
  • the embodiment of the invention further provides a device for power failure protection, which is applied to an electronic device, as shown in FIG. 4 and FIG. 5, comprising: a power supply unit 01, a voltage monitoring unit 02, a processor unit 03, and a field programmable gate array.
  • the voltage monitoring unit 02 is configured to monitor an electrical signal output by the power source, and when the fluctuation of the electrical signal is detected to be within a threshold range, output a first indication signal as a power failure indication signal, when the fluctuation of the electrical signal is detected When the threshold range is exceeded, a second indication signal as a power down indication signal is output.
  • the FPGA 04 is configured to, when detecting the outputting the second indication signal, write data synchronized with the processor unit 03 and current system time to the non-volatile flash memory, and on the next time the electronic device The stored data synchronized with the processor unit is loaded after being powered.
  • the technology provided by the application after the power is turned off, the data is stored outside the CPU, and the data is pre-backup in the internal register of the FPGA or the internal random access memory.
  • the FPGA directly writes the data into the built-in FLash, and implements the data more quickly than the pure software method. Storage; no intervention from CPU and operating system is required. After power failure, the storage capacitor only needs to supply power to the FPGA, save power, and have low requirements on capacitor capacity. It can ensure that important data is safely recorded in the environment where the power supply is unexpectedly powered down. And the implementation cost is low.
  • the processor unit 03 may be a Central Processing Unit (CPU).
  • CPU Central Processing Unit
  • the power supply unit 01 supplies power to the entire electronic device, and the input is commercial power or industrial power, and is converted into a DC voltage output through a DC stabilized power supply.
  • the power supply unit may be subject to external disturbances that cause power fluctuations or unexpected power outages.
  • the voltage monitoring unit 02 is implemented by an analog circuit and is configured to monitor the fluctuation range of the output voltage of the power supply unit and give a power down indication signal.
  • the output power-down indication signal is a high level, and when the fluctuation of the voltage is detected to exceed the threshold value - the main direction downward fluctuation exceeds the threshold value, the output power-down indication signal Is low.
  • FPGA 04 which contains a storage subsystem, is set up to store and return protected data.
  • the FPGA uses XILINX's Spartan-3AN series FPGA, which has its own non-volatile Flash, with a capacity of up to 11Mb, and plenty of space to store protected data.
  • the use of this built-in Flash FPGA not only saves cost, reduces PCB layout area, but also reduces power consumption compared to using two discrete devices, which is especially important for power supply after power-down.
  • the storage subsystem is Flash, a non-volatile memory that can erase and reprogram the address space of a minimum of one page (256 Bytes).
  • An erase operation is required before programming the memory space.
  • the erase operation takes a long time relative to the write operation. Taking the Spartan-3AN built-in Flash as an example, erasing a page takes about 32 to 35 milliseconds, and writing a page takes 4 to 6 milliseconds.
  • the invention adopts a pre-erase method to ensure that the FPGA only needs to write to the erased address after the power is turned off, and the processor unit controls the FPGA to implement the pre-erase. When the power supply fluctuates beyond the threshold, the FPGA receives the power-down indication signal to a low level and initiates a Flash write operation.
  • the electrical signal is a voltage; the first indication signal is a high level; and the second indication signal is a low level.
  • the voltage monitoring unit 02 includes:
  • the power-down indication module 021 is configured to adopt a voltage as the electrical signal.
  • the output power-down indication signal is a high level, and when the monitored voltage fluctuation exceeds a threshold range, the output is output.
  • the power down indication signal is low.
  • the device further includes: a storage capacitor 05.
  • the processor unit 03 is configured to write state data, operation data and memory data generated when the system software is running and needs to be protected into the FPGA internal register or the internal random access memory; and write the current system time into the FPGA internal register, and the FPGA starts The internal system is timed and waits for the power to be powered down.
  • the storage capacitor 05 is set to supply power to the FPGA after the power supply has been powered down.
  • FPGA 04 is also configured to write the status data, operational data, memory data, and system time at power down to the non-volatile flash memory after the system is powered down.
  • the processor unit 03 is configured to: when the second indication signal is detected to be output, if the power supply is not actually powered down, and the operation of the system software of the electronic device is not affected, then the field programmable gate array unit FPGA wipe is controlled. In addition to the corresponding address in Flash, wait for the power supply to power down again.
  • the power supply unit 01 has an output voltage VO higher than the lower limit value VL of the normal operating voltage of the FPGA, which is lower than the upper limit value VH, and the threshold is set between the power supply output voltage VO and the lower voltage VL of the normal operation of the FPGA.
  • the storage capacitor can begin to supply power at a minimum voltage that is higher than the normal operation of the FPGA.
  • the threshold and the capacity of the storage capacitor need to be balanced to ensure that the threshold is not set too high and the operation is not caused, and the storage capacity is not increased because the storage capacitor is too large.
  • the field programmable gate array unit FPGA 04 is further configured to: after the electronic device is started, the FPGA reads the state data, the operation data, and the memory data stored in the Flash after the last power-down, into the FPGA internal register or Internal random access memory.
  • the processor unit 03 is further arranged to read the internal registers of the FPGA or the internal random access memory through the data read channel to recover the data.
  • FPGA 04 is also set to read the data through the data read channel, then the Flash will be The address space corresponding to the data is erased.
  • the embodiment of the present invention further provides an electronic device, including the above device for power failure protection.
  • the device for power failure protection includes: a power supply unit 01, a voltage monitoring unit 02, a processor unit 03, and an on-site Programming gate array unit FPGA 04;
  • the voltage monitoring unit 02 is configured to monitor an electrical signal output by the power source, and when the fluctuation of the electrical signal is within a threshold range, output a first indication signal as a power failure indication signal, when the fluctuation of the electrical signal exceeds the threshold range Outputting a second indication signal as a power down indication signal;
  • the field programmable gate array unit FPGA 04 is configured to write the data synchronized with the processor unit and the current system time to the non-volatile flash memory when the second indication signal is present, and power on the electronic device next time. After loading.
  • the advantage after adopting this scheme is that the data storage is performed outside the processor unit after power-off, which reduces the operation of the processor unit and the operating system after power-off, and is faster than the pure software protection method, and can ensure that the power supply is unexpectedly powered down.
  • the data is safely recorded, saving power and enabling instant storage of data.
  • a computer readable storage medium storing computer executable instructions that, when executed by a processor, implement the power down protection method.
  • all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
  • the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
  • the device/function module/functional unit in the above embodiment When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium.
  • the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • the device of the embodiment of the invention performs data storage outside the processor unit after power-off, which reduces the operation of the processor unit and the operating system after power-off, and is faster than the pure software protection method, and can ensure the environment in the case of unexpected power failure. Record data securely, conserve power and store data instantly.

Abstract

A power-down protection method and apparatus, and an electronic device. The method is applied to the electronic device. The electronic device comprises a field programmable gate array (FPGA) unit. The method comprises: monitoring an electrical signal output by a power source, and when it is monitored that the fluctuation of the electrical signal is within a threshold value range, outputting a power-down indication signal marked as a first indication signal, and when it is monitored that the fluctuation of the electrical signal is beyond the threshold value range, outputting a power-down indication signal marked as a second indication signal (S101); and when it is monitored that the second indication signal is output, writing data synchronized with a processor unit, and a current system time into a non-volatile flash memory (Flash), and loading the stored data synchronized with the processor unit after the next power-on of the electronic device (S102).

Description

一种掉电保护的方法、装置和电子设备Method, device and electronic device for power failure protection 技术领域Technical field
本申请涉及但不限于电子设备掉电技术,尤其涉及一种掉电保护的方法、装置和电子设备。The present application relates to, but is not limited to, an electronic device power-down technology, and more particularly to a method, device, and electronic device for power-down protection.
背景技术Background technique
掉电保护的目的是在系统失去供电的情况下,采用一种机制来保证系统运行状态的确定性和记录数据的完整性;当系统恢复供电后,能够及时恢复系统的现场数据,避免系统产生混乱。The purpose of power-down protection is to use a mechanism to ensure the certainty of the operating state of the system and the integrity of the recorded data when the system loses power. When the system resumes power supply, it can restore the system's field data in time to avoid system generation. confusion.
相关技术一般采用备用电源和电池续电来应对电源意外掉电。理想情况下,采用备用电源能够实现主、备电源之间的无缝切换,是一种比较安全的应对措施,但是额外的备用电源增加了成本;采用电池续电能够保证在电池续航时间内完整地保存数据,但是电池的寿命有限,同样面临着增加成本的问题。Related technologies generally use backup power and battery power to cope with power failure. Ideally, the use of a backup power supply enables seamless switching between the primary and backup power supplies. This is a relatively safe response, but the additional backup power supply adds cost; battery life is guaranteed to be complete during battery life. Data is saved, but the battery life is limited, and it also faces the problem of increasing costs.
相关采用纯软件方式进行掉电保护的技术存在如下问题:当检测到掉电时,触发中断,将运行数据写入非易失性存储器。当软件系统较复杂,特别是引入了操作系统,采用基于文件读写的方式操作数据,数据量一般比较大,进行数据的保护操作耗时较长,对供电电源要求较高,储能电容显然不再合适,因此基于纯软件方式进行掉电保护已经不再可靠。The related technology that uses the pure software mode for power-down protection has the following problems: When a power failure is detected, an interrupt is triggered, and the running data is written into the non-volatile memory. When the software system is more complicated, especially the operating system is introduced, the data is operated by means of file reading and writing. The data volume is generally large, and the data protection operation takes a long time. The power supply requirement is high, and the storage capacitor is obviously No longer suitable, so power-down protection based on software-only is no longer reliable.
发明内容Summary of the invention
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。The following is an overview of the topics detailed in this document. This Summary is not intended to limit the scope of the claims.
本发明实施例要解决的技术问题是提供一种掉电保护的方法、装置和电子设备,用于解决相关技术中基于纯软件方式进行掉电保护已经不再可靠的缺陷。The technical problem to be solved by the embodiments of the present invention is to provide a method, a device, and an electronic device for power-down protection, which are used to solve the defects in the related art that the power-down protection based on the pure software mode is no longer reliable.
一种掉电保护的方法,应用于电子设备,所述电子设备包括现场可编程门阵列单元FPGA,该方法包括:监测电源输出的电信号;当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当 监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号;当监测到输出所述第二指示信号时,将与处理器单元同步的数据和当前系统时间写入非易失性闪存Flash,并在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据。A method for power-down protection is applied to an electronic device, the electronic device comprising a field programmable gate array unit FPGA, the method comprising: monitoring an electrical signal output by the power source; and detecting that the fluctuation of the electrical signal is within a threshold range When outputting the first indication signal as the power down indication signal, when And detecting, when the fluctuation of the electrical signal exceeds the threshold range, outputting a second indication signal as a power down indication signal; when monitoring the outputting the second indication signal, synchronizing data with the processor unit and the current system The time is written to the non-volatile flash memory and the stored data synchronized with the processor unit is loaded after the electronic device is powered up next time.
可选地,所述电信号为电压;所述第一指示信号为高电平;所述第二指示信号为低电平;Optionally, the electrical signal is a voltage; the first indication signal is a high level; and the second indication signal is a low level;
当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号包括:当监测到所述电压的波动在所述阈值范围内时,输出高电平,当监测到所述电压的波动超过阈值范围时,输出低电平。When it is detected that the fluctuation of the electrical signal is within a threshold range, outputting a first indication signal as a power-down indication signal, and when detecting that the fluctuation of the electrical signal exceeds the threshold range, outputting as a power-down indication signal The second indication signal includes: outputting a high level when the fluctuation of the voltage is detected within the threshold range, and outputting a low level when detecting that the fluctuation of the voltage exceeds a threshold range.
可选地,电信号的波动超过所述阈值范围包括:电源输出的电信号向下波动超过所述阈值范围的下限阈值。Optionally, the fluctuation of the electrical signal exceeding the threshold range includes that the electrical signal output by the power supply fluctuates downward beyond a lower threshold of the threshold range.
可选地,将与处理器单元同步的数据和当前系统时间写入非易失性闪存Flash包括:Optionally, writing data synchronized with the processor unit and current system time to the non-volatile flash memory includes:
由处理器单元将系统软件运行时产生且需要保护的状态数据、运算数据和内存数据均写入FPGA内部寄存器或者内部随机存储器;以及,由处理器单元将当前系统时间写入FPGA内部寄存器,FPGA启动内部系统计时,等待电源发生掉电;电源发生掉电之后,由储能电容对FPGA供电,由FPGA在系统掉电后将所述状态数据、运算数据、内存数据和掉电时系统时间写入FPGA内置的非易失性闪存Flash。The state data, the operation data and the memory data generated by the system software and required to be protected by the processor unit are written into the FPGA internal register or the internal random access memory; and the current system time is written by the processor unit into the FPGA internal register, the FPGA Start the internal system timing, wait for the power supply to be powered down; after the power supply is powered off, the FPGA supplies power to the FPGA by the storage capacitor. The FPGA writes the status data, operation data, memory data, and system time when the system is powered down. Into the non-volatile flash memory built into the FPGA.
可选地,所述方法还包括:当监测到输出所述第二指示信号时,如果电源未实际掉电,且电子设备的软件的工作未受影响,则由处理器单元控制FPGA擦除非易失性闪存中的相应地址,再次等待电源发生掉电。Optionally, the method further includes: when detecting the outputting the second indication signal, if the power supply is not actually powered down, and the software of the electronic device is not affected, the processor unit controls the FPGA to erase the non-easy The corresponding address in the flash memory, again waiting for the power to be powered down.
可选地,所述在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据包括:在电子设备启动后,FPGA将上次掉电后保存在所述非易失性闪存中的被保护数据读入FPGA内部寄存器或者内部随机存储器,由处理器单元通过数据读取通道读取FPGA的内部寄存器或者内部随机存储器,恢复所述数据; Optionally, the loading the stored data synchronized with the processor unit after the next power-on of the electronic device comprises: after the electronic device is started, the FPGA saves the non-volatile after the last power-down The protected data in the flash memory is read into the FPGA internal register or the internal random access memory, and the processor unit reads the internal register of the FPGA or the internal random access memory through the data read channel to recover the data;
通过数据读取通道读取数据完毕后,FPGA将Flash中与所述数据对应的地址空间擦除。After the data is read through the data read channel, the FPGA erases the address space corresponding to the data in the flash.
一种掉电保护的装置,应用于电子设备,包括:电压监测单元、现场可编程门阵列单元FPGA和处理器单元;A device for power failure protection, applied to an electronic device, comprising: a voltage monitoring unit, a field programmable gate array unit FPGA and a processor unit;
电压监测单元,设置为监测电源输出的电信号,当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号。a voltage monitoring unit configured to monitor an electrical signal output by the power source, and when detecting that the fluctuation of the electrical signal is within a threshold range, outputting a first indication signal as a power failure indication signal, when the fluctuation of the electrical signal is detected to exceed In the threshold range, a second indication signal is output as a power down indication signal.
FPGA,设置为当检测到输出所述第二指示信号时,将与处理器单元同步的数据和当前系统时间写入非易失性闪存Flash,并在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据。The FPGA is configured to, when detecting the outputting the second indication signal, write data synchronized with the processor unit and current system time to the non-volatile flash memory, and load the storage after the electronic device is powered on next time The data synchronized with the processor unit.
可选地,所述电信号为电压;所述第一指示信号为高电平;所述第二指示信号为低电平;电压监测单元包括:掉电指示模块,设置为当监测到所述电压的波动在所述阈值范围内时,输出高电平,当监测到所述电压波动超过所述阈值范围时,输出低电平。Optionally, the electrical signal is a voltage; the first indication signal is a high level; the second indication signal is a low level; and the voltage monitoring unit includes: a power down indication module, configured to monitor the When the fluctuation of the voltage is within the threshold range, a high level is output, and when the voltage fluctuation is detected to exceed the threshold range, a low level is output.
可选地,所述电信号的波动超过所述阈值范围包括:电源输出的电信号向下波动超过所述阈值范围的下限阈值。Optionally, the fluctuation of the electrical signal exceeding the threshold range includes: the electrical signal output by the power source fluctuates downward beyond a lower threshold of the threshold range.
可选地,所述装置还包括:储能电容。处理器单元,设置为将系统软件运行时产生的被保护数据均写入FPGA内部寄存器或者内部随机存储器;以及,将当前系统时间写入FPGA内部寄存器,FPGA启动内部系统计时,等待电源发生掉电;储能电容,设置为在电源发生掉电之后,对FPGA供电;FPGA,还设置为在系统掉电后将所述状态数据、运算数据、内存数据和掉电时系统时间写入非易失性闪存Flash。Optionally, the device further includes: a storage capacitor. The processor unit is configured to write the protected data generated when the system software is running into the FPGA internal register or the internal random access memory; and, write the current system time into the FPGA internal register, and the FPGA starts the internal system timing, waiting for the power supply to be powered down. The storage capacitor is set to supply power to the FPGA after the power supply is powered off; the FPGA is also configured to write the state data, the operation data, the memory data, and the system time when the power is off after the system is powered down. Flash Flash.
可选地,处理器单元,设置为当监测到输出所述第二指示信号时,如果电源未实际掉电,且电子设备的软件的工作未受影响,则控制所述FPGA擦除非易失性闪存中的相应地址,再次等待电源发生掉电。Optionally, the processor unit is configured to control the FPGA to erase non-volatile if the power is not actually powered down and the operation of the software of the electronic device is not affected when the second indication signal is detected to be output. The corresponding address in the flash memory, again waiting for the power to be powered down.
可选地,所述FPGA,还设置为在电子设备启动后,FPGA将上次掉电后保存在所述非易失性闪存中的被保护数据读入FPGA内部寄存器或者内部随机存储器;所述处理器单元还设置为,通过数据读取通道读取FPGA的内部 寄存器或者内部随机存储器,恢复所述数据;Optionally, the FPGA is further configured to: after the electronic device is started, the FPGA reads the protected data saved in the non-volatile flash memory after the last power-down into the FPGA internal register or the internal random access memory; The processor unit is also configured to read the interior of the FPGA through the data read channel a register or an internal random access memory to recover the data;
所述FPGA还设置为,通过数据读取通道读取数据完毕后,将所述Flash中与所述数据对应的地址空间擦除。The FPGA is further configured to erase the address space corresponding to the data in the Flash after the data is read through the data read channel.
一种电子设备,包括上述的掉电保护的装置。An electronic device comprising the above-described device for power-down protection.
一种计算机可读存储介质,存储有计算机可执行指令,所述计算机可执行指令被处理器执行时实现所述的掉电保护方法。A computer readable storage medium storing computer executable instructions that, when executed by a processor, implement the power down protection method.
本发明实施例方案的有益效果如下:掉电后在处理器单元外部执行数据的存储,减少了掉电后处理器单元和操作系统的操作,较纯软件保护方法更快速,能够保证在电源意外掉电的环境下将数据安全地记录下来,节省电量且能够即时存储数据。The beneficial effects of the solution of the embodiment of the present invention are as follows: the data storage is performed outside the processor unit after the power is turned off, the operation of the processor unit and the operating system after the power failure is reduced, and the pure software protection method is faster, and the power supply accident can be ensured. Data is safely recorded in a power-down environment, conserving power and enabling instant storage of data.
附图概述BRIEF abstract
图1为本发明实施例的一种掉电保护的方法的流程示意图;1 is a schematic flow chart of a method for power failure protection according to an embodiment of the present invention;
图2为本发明实施例的电子设备在发生掉电之前以及掉电后的工作过程示意图;2 is a schematic diagram of a working process of an electronic device before powering down and after power-off according to an embodiment of the present invention;
图3为本发明实施例的电子设备上电之后的工作流程示意图;3 is a schematic diagram of a workflow after an electronic device is powered on according to an embodiment of the present invention;
图4为本发明实施例的一种掉电保护的装置及电子设备的结构示意图;4 is a schematic structural diagram of a device and an electronic device for power failure protection according to an embodiment of the present invention;
图5为本发明实施例的一种掉电保护的装置结构组成框图。FIG. 5 is a structural block diagram of a device for power failure protection according to an embodiment of the present invention.
本发明的实施方式Embodiments of the invention
下文中将参考附图并结合实施例来详细说明本申请。需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。The present application will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.
本发明实施例提供一种掉电保护的方法,应用于电子设备,如图1所示,所述电子设备包括现场可编程门阵列(FPGA,Field-Programmable Gate Array),方法包括步骤S101-S102:An embodiment of the present invention provides a method for power-down protection, which is applied to an electronic device. As shown in FIG. 1 , the electronic device includes a Field-Programmable Gate Array (FPGA), and the method includes steps S101-S102. :
S101、监测电源输出的电信号,当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号。S101. Monitor an electrical signal output by the power source, and when detecting that the fluctuation of the electrical signal is within a threshold range, output a first indication signal as a power-down indication signal, when the fluctuation of the monitored electrical signal exceeds the threshold range, A second indication signal is output as a power down indication signal.
S102、当监测到输出所述第二指示信号时,将与处理器单元同步的数据 和当前系统时间写入非易失性闪存Flash,并在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据。S102. When monitoring the outputting the second indication signal, synchronizing data with the processor unit And writing the non-volatile flash memory with the current system time, and loading the stored data synchronized with the processor unit after the electronic device is powered up next time.
应用所提供的技术方案,掉电后在CPU外部执行数据的存储,数据预先备份在FPGA的内部寄存器或者内部随机存储器中,FPGA直接将数据写入内置FLash,较纯软件方法更快速地实现数据的存储;不需要CPU及操作系统的干预,掉电后储能电容只需对FPGA供电,节省电量,对电容容量要求低;能够保证在电源意外掉电的环境下将重要数据安全地记录下来,而且实现成本低。软件指CPU运行的系统软件,一般指操作系统(OS)。The technical solution provided by the application, after the power is turned off, the data is stored outside the CPU, and the data is pre-backup in the internal register of the FPGA or the internal random access memory. The FPGA directly writes the data into the built-in FLash, and implements the data more quickly than the pure software method. Storage; no CPU and operating system intervention is required. After power failure, the storage capacitor only needs to supply power to the FPGA, save power, and have low capacitance requirements. It can ensure that important data is safely recorded in the environment of unexpected power failure. And the implementation cost is low. Software refers to the system software that the CPU runs, generally referring to the operating system (OS).
FPGA及FPGA的存储子系统(非易失性Flash)用来存储和回送被保护的数据。FPGA选用XILINX的Spartan-3AN系列FPGA,其内部自带内部寄存器或者内部随机存储器,以及非易失性Flash,非易失性Flash的存储空间达11Mb,有充足的空间存储被保护的数据。选用这种内置Flash的FPGA不但节约了成本、减小PCB布板面积,而且比采用两块分立器件减少了电能消耗,这对掉电后依靠储能电容供电来说尤为重要。The storage subsystem (non-volatile Flash) of the FPGA and FPGA is used to store and return protected data. The FPGA uses XILINX's Spartan-3AN series FPGA, which has its own internal registers or internal random access memory, as well as non-volatile Flash. The non-volatile flash has a storage space of 11Mb and has enough space to store protected data. The use of this built-in Flash FPGA not only saves cost, reduces PCB layout area, but also reduces power consumption compared to using two discrete devices, which is especially important for power supply after power-down.
FPGA内部的Flash作为一种非易失性存储器,可以对最小单位一页(256Bytes)的地址空间进行擦除和再编程。在对存储空间进行编程之前需要进行擦除操作,相对于写入操作来说,擦除操作耗时较长。以Spartan-3AN系列FPGA内置的Flash为例,写入一页耗时4~6毫秒,擦除一页耗时约32~35毫秒。本发明实施例采用预先擦除的方式,由CPU控制FPGA来实现预先擦除,保证在掉电之后FPGA只需要进行写入操作。当电源电压的波动超过阈值时,FPGA收到的掉电指示信号为低电平,启动Flash写入操作。The internal Flash of the FPGA acts as a non-volatile memory that can erase and reprogram the address space of a minimum of one page (256 Bytes). An erase operation is required before the memory space is programmed, and the erase operation takes a long time relative to the write operation. Taking the Flash built in the Spartan-3AN series FPGA as an example, writing a page takes 4 to 6 milliseconds, and erasing a page takes about 32 to 35 milliseconds. In the embodiment of the invention, the pre-erase is implemented by the CPU controlling the FPGA in a pre-erase manner to ensure that the FPGA only needs to perform a write operation after the power is turned off. When the fluctuation of the power supply voltage exceeds the threshold, the power-down indication signal received by the FPGA is low, and the Flash write operation is started.
可选地,Optionally,
所述电信号为电压;所述第一指示信号为高电平;所述第二指示信号为低电平;The electrical signal is a voltage; the first indication signal is a high level; and the second indication signal is a low level;
当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号包括:当监测到所述电压的波动在所述阈值范围内时,输出高电平,当监测到所述电压的波动超过阈值范围时,输出低电平。 When it is detected that the fluctuation of the electrical signal is within a threshold range, outputting a first indication signal as a power-down indication signal, and when detecting that the fluctuation of the electrical signal exceeds the threshold range, outputting as a power-down indication signal The second indication signal includes: outputting a high level when the fluctuation of the voltage is detected within the threshold range, and outputting a low level when detecting that the fluctuation of the voltage exceeds a threshold range.
采用电压作为所述电信号,当电压的波动在阈值范围内时,掉电指示信号输出高电平作为第一指示信号,当电压波动超过阈值范围时,掉电指示信号输出低电平作为第二指示信号。所述阈值范围存在一个上限阈值和一个下限阈值。The voltage is used as the electrical signal. When the voltage fluctuation is within the threshold range, the power-down indication signal outputs a high level as the first indication signal. When the voltage fluctuation exceeds the threshold range, the power-down indication signal outputs a low level as the first Two indication signals. The threshold range has an upper threshold and a lower threshold.
可选地,电信号的波动超过阈值范围具体是指电信号向下波动超过所述阈值范围的下限阈值。Optionally, the fluctuation of the electrical signal exceeding the threshold range specifically refers to the lower threshold of the electrical signal fluctuating downward beyond the threshold range.
FPGA将通过数据备份通道写入其内部寄存器或者内部随机存储器的被保护数据和内部系统时间写入非易失性闪存(Flash)。可选地,将与处理器单元同步的数据和当前系统时间写入非易失性闪存Flash包括:The FPGA writes the protected data and its internal system time written to its internal registers or internal random access memory through the data backup channel to the non-volatile flash memory (Flash). Optionally, writing data synchronized with the processor unit and current system time to the non-volatile flash memory includes:
由处理器单元将系统软件运行时产生的被保护数据均写入FPGA内部寄存器或者内部随机存储器;以及,由处理器单元将当前系统时间写入FPGA内部寄存器,FPGA启动内部系统计时,等待电源发生掉电。The protected data generated by the system software when the system software is running is written into the FPGA internal register or the internal random access memory by the processor unit; and, by the processor unit, the current system time is written into the FPGA internal register, and the FPGA starts the internal system timing, waiting for the power supply to occur. Power down.
电源发生掉电之后,由储能电容对FPGA供电,由FPGA在系统掉电后将所述状态数据、运算数据、内存数据和掉电时系统时间写入非易失性闪存Flash。After the power supply is powered off, the FPGA is powered by the storage capacitor. The FPGA writes the status data, operation data, memory data, and system time during power-down to the non-volatile flash memory after the system is powered down.
其中,状态数据、运算数据和内存数据均是所述被保护数据。The status data, the operation data, and the memory data are all the protected data.
电源掉电之后,在FPGA写数据期间由储能电容对FPGA供电,FPGA捕捉到掉电指示信号为低电平,将所述通过数据备份通道写入其内部寄存器或者内部随机存储器的被保护数据和内部系统时间一同写入Flash。After the power supply is powered off, the FPGA is powered by the storage capacitor during the data write of the FPGA. The FPGA captures the power-down indication signal to a low level, and writes the protected data through the data backup channel to its internal register or internal random access memory. Write to Flash along with the internal system time.
可选地,所述方法还包括:当监测到输出所述第二指示信号时,如果电源未实际掉电,且电子设备的软件的工作未受影响,则由处理器单元控制FPGA擦除Flash中的相应地址,再次等待电源发生掉电。这一过程中,掉电指示信号为低电平,但实际电源并未掉电,电子设备的操作系统仍然正常运行,则CPU控制FPGA擦除Flash中的相应地址,再次等待电源发生掉电。Optionally, the method further includes: when monitoring the outputting the second indication signal, if the power supply is not actually powered down, and the operation of the software of the electronic device is not affected, the processor unit controls the FPGA to erase the Flash. The corresponding address in the middle, wait for the power supply to power down again. In this process, the power-down indication signal is low, but the actual power supply is not powered down, and the operating system of the electronic device is still running normally, then the CPU controls the FPGA to erase the corresponding address in the Flash, and waits for the power supply to be powered down again.
可选地,在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据包括:Optionally, loading the stored data synchronized with the processor unit after the next power-on of the electronic device includes:
在电子设备启动后,FPGA将上次掉电后保存在所述Flash中的状态数据、运算数据和内存数据读入FPGA内部寄存器或者内部随机存储器,由处理器单元通过数据读取通道读取FPGA的内部寄存器或者内部随机存储器,恢复 所述数据;After the electronic device is started, the FPGA reads the state data, the operation data, and the memory data stored in the Flash after the last power-down, and reads the FPGA into the internal register or the internal random memory, and the processor unit reads the FPGA through the data read channel. Internal register or internal random access memory, recovery The data;
通过数据读取通道读取数据完毕后,FPGA将Flash的与所述数据对应的地址空间擦除。After the data is read through the data read channel, the FPGA erases the address space corresponding to the data of the flash.
本发明实施例提出了一种基于内置Flash的FPGA实现掉电保护数据的实现方法,能够在电源掉电后的数十毫秒之内,将掉电时的当前系统时间、被保护数据写入FPGA内置的Flash中,电子设备再次上电时,FPGA读取Flash中的数据,再由CPU回读FPGA数据,达到重要数据在断电时得到安全保存的目的。The embodiment of the invention provides an implementation method for implementing power-down protection data based on an FPGA built in Flash, which can write the current system time and protected data in the power failure to the FPGA within tens of milliseconds after the power is turned off. In the built-in Flash, when the electronic device is powered on again, the FPGA reads the data in the Flash, and then the CPU reads back the FPGA data, so that the important data is safely saved when the power is turned off.
如图2所示,电子设备在掉电之前以及发生掉电时的工作过程包括步骤S201-S206:As shown in FIG. 2, the working process of the electronic device before power failure and when power failure occurs includes steps S201-S206:
步骤201,对电源输出的电信号所产生的波动进行监控,一般是采用电压作为所述电信号。In step 201, the fluctuation generated by the electrical signal output by the power source is monitored, and generally the voltage is used as the electrical signal.
步骤202,判断电压的波动是否超过阈值范围,当电压的波动超过阈值时,转步骤203,当电压的波动未超过阈值时转步骤201。Step 202: Determine whether the fluctuation of the voltage exceeds the threshold range. When the fluctuation of the voltage exceeds the threshold, the process proceeds to step 203, and when the fluctuation of the voltage does not exceed the threshold, the process proceeds to step 201.
步骤203,FPGA收到掉电指示信号为低,表示电压的波动超过阈值,将与处理器单元CPU同步的数据和当前时间写入Flash。Step 203: The FPGA receives the power-down indication signal to be low, indicating that the voltage fluctuation exceeds the threshold, and the data synchronized with the processor unit CPU and the current time are written into the Flash.
步骤204,判断电源是否实际上确实掉电了,如果判定电源确实掉电了则转步骤206,如果判定电源实际上并未掉电则转步骤205。In step 204, it is determined whether the power source is actually powered down. If it is determined that the power source is indeed powered down, then step 206 is performed. If it is determined that the power source is not actually powered down, then step 205 is performed.
步骤205,电源波动超过阈值,但是实际上,电源可能并未掉电,系统软件并未停止工作;为防止此类误操作,CPU控制FPGA重新擦除内置的Flash;转步骤201。 Step 205, the power supply fluctuation exceeds the threshold, but in fact, the power supply may not be powered down, and the system software does not stop working; to prevent such misoperation, the CPU controls the FPGA to erase the built-in Flash again;
步骤206,电源系统确实掉电了,再次上电时执行电子设备系统上电的工作流程。In step 206, the power system is powered off, and the power-on workflow of the electronic device system is executed when the power is turned on again.
如图3所示,电子设备上电之后的工作流程包括步骤S301-S307:As shown in FIG. 3, the workflow after the electronic device is powered on includes steps S301-S307:
步骤301,电子设备上电启动,FPGA就绪后读取内置Flash中的被保护数据到FPGA的内部寄存器或者内部随机存储器。 Step 301, the electronic device is powered on, and the protected data in the built-in flash is read into an internal register of the FPGA or an internal random access memory after the FPGA is ready.
步骤302,处理器单元CPU通过数据读取通道读取FPGA的内部寄存器或者内部随机存储器,获取上次掉电时保存的被保护数据。Step 302: The processor unit CPU reads an internal register of the FPGA or an internal random access memory through the data read channel, and acquires the protected data saved when the power is last powered off.
步骤303,CPU完成读取被保护数据,以及控制FPGA擦除Flash该地址 区域的数据。 Step 303, the CPU finishes reading the protected data, and controls the FPGA to erase the flash address. Regional data.
之后的步骤,就是电子设备在正常工作状态下,为下一次可能发生的掉电事件进行前期准备。The next step is to prepare the electronic device for the next possible power failure event under normal working conditions.
步骤304,为保证被保护数据的实时性和准确性,在正常工作状态下,由处理器单元将当前系统时间写入FPGA,FPGA启动内部计时,采用高精度的晶振保证FPGA内部系统时间与真实系统时间保持较小的误差。Step 304, in order to ensure the real-time and accuracy of the protected data, in the normal working state, the current unit time is written into the FPGA by the processor unit, the FPGA starts the internal timing, and the high-precision crystal oscillator is used to ensure the internal system time and reality of the FPGA. System time keeps small errors.
同理,掉电时将掉电时间和被保护数据一起写入Flash:电源掉电导致处理器单元瞬间停止工作,外部系统时间丢失,FPGA将内部系统时间写入Flash。Similarly, when power is off, the power-down time is written to the flash together with the protected data: the power supply is powered down, causing the processor unit to stop working momentarily, the external system time is lost, and the FPGA writes the internal system time to Flash.
步骤305,FPGA收到CPU下发的系统时间后开始启动计时,采用精确计时保证与系统时间同步。In step 305, the FPGA starts to start timing after receiving the system time sent by the CPU, and uses precise timing to ensure synchronization with the system time.
步骤306,CPU在运行时将需要保护的数据通过数据备份通道写入FPGA内部寄存器或者内部随机存储器,保证重要数据在FPGA中实时备份,这包括: Step 306, the CPU writes the data to be protected to the FPGA internal register or the internal random access memory through the data backup channel during operation to ensure that important data is backed up in real time in the FPGA, including:
处理器单元将系统软件运行时产生且需要保护的状态数据、运算数据和内存数据均写入FPGA内部寄存器或者内部随机存储器;以及,处理器单元将当前系统时间写入FPGA内部寄存器,FPGA启动内部系统计时,等待电源发生掉电。电源发生掉电之后,由储能电容对FPGA供电,由FPGA在系统掉电后将所述状态数据、运算数据、内存数据和掉电时系统时间写入非易失性闪存Flash。The processor unit writes state data, operation data and memory data generated by the system software and needs to be protected into the FPGA internal register or the internal random access memory; and the processor unit writes the current system time to the FPGA internal register, and the FPGA starts the internal The system clocks and waits for the power to be powered down. After the power supply is powered off, the FPGA is powered by the storage capacitor. The FPGA writes the status data, operation data, memory data, and system time during power-down to the non-volatile flash memory after the system is powered down.
步骤307,电子设备准备就绪,等待电源再次发生掉电。In step 307, the electronic device is ready to wait for the power to be powered down again.
本发明实施例还提供了一种掉电保护的装置,应用于电子设备,如图4、图5所示,包括:电源单元01、电压监测单元02、处理器单元03、现场可编程门阵列单元FPGA 04。The embodiment of the invention further provides a device for power failure protection, which is applied to an electronic device, as shown in FIG. 4 and FIG. 5, comprising: a power supply unit 01, a voltage monitoring unit 02, a processor unit 03, and a field programmable gate array. Unit FPGA 04.
电压监测单元02,设置为监测电源输出的电信号,当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号。 The voltage monitoring unit 02 is configured to monitor an electrical signal output by the power source, and when the fluctuation of the electrical signal is detected to be within a threshold range, output a first indication signal as a power failure indication signal, when the fluctuation of the electrical signal is detected When the threshold range is exceeded, a second indication signal as a power down indication signal is output.
所述FPGA 04,设置为当检测到输出所述第二指示信号时,将与处理器单元03同步的数据和当前系统时间写入非易失性闪存Flash,并在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据。The FPGA 04 is configured to, when detecting the outputting the second indication signal, write data synchronized with the processor unit 03 and current system time to the non-volatile flash memory, and on the next time the electronic device The stored data synchronized with the processor unit is loaded after being powered.
应用所提供的技术,掉电后在CPU外部执行数据的存储,数据预先备份在FPGA的内部寄存器或者内部随机存储器中,FPGA直接将数据写入内置FLash,较纯软件方法更快速地实现数据的存储;不需要CPU及操作系统的干预,掉电后储能电容只需对FPGA供电,节省电量,对电容容量要求低;能够保证在电源意外掉电的环境下将重要数据安全地记录下来,而且实现成本低。The technology provided by the application, after the power is turned off, the data is stored outside the CPU, and the data is pre-backup in the internal register of the FPGA or the internal random access memory. The FPGA directly writes the data into the built-in FLash, and implements the data more quickly than the pure software method. Storage; no intervention from CPU and operating system is required. After power failure, the storage capacitor only needs to supply power to the FPGA, save power, and have low requirements on capacitor capacity. It can ensure that important data is safely recorded in the environment where the power supply is unexpectedly powered down. And the implementation cost is low.
处理器单元03可以是中央处理器(CPU,Central Processing Unit)。The processor unit 03 may be a Central Processing Unit (CPU).
电源单元01,为整个电子设备供电,输入为市电或工业用电,经过直流稳压电源,转换为直流电压输出。电源单元可能受到外界干扰导致电源波动,或者遭受意外断电。The power supply unit 01 supplies power to the entire electronic device, and the input is commercial power or industrial power, and is converted into a DC voltage output through a DC stabilized power supply. The power supply unit may be subject to external disturbances that cause power fluctuations or unexpected power outages.
电压监测单元02,由模拟电路实现,设置为为电源单元输出电压的波动范围进行监测,并给出掉电指示信号。当监测到所述电压波动在正常的阈值范围内时,输出的掉电指示信号是高电平,当监测到所述电压的波动超过阈值-主要指向下波动超过阈值,输出的掉电指示信号是低电平。The voltage monitoring unit 02 is implemented by an analog circuit and is configured to monitor the fluctuation range of the output voltage of the power supply unit and give a power down indication signal. When it is detected that the voltage fluctuation is within a normal threshold range, the output power-down indication signal is a high level, and when the fluctuation of the voltage is detected to exceed the threshold value - the main direction downward fluctuation exceeds the threshold value, the output power-down indication signal Is low.
FPGA 04,包含存储子系统,设置为存储和回送被保护数据。FPGA选用XILINX的Spartan-3AN系列FPGA,其内部自带非易失性Flash,容量多达11Mb,有充足的空间来存储被保护数据。选用这种内置Flash的FPGA不但节约了成本、减小PCB布板面积,而且比采用两块分立器件减少了电能消耗,这对掉电后依靠储能电容供电来说尤为重要。FPGA 04, which contains a storage subsystem, is set up to store and return protected data. The FPGA uses XILINX's Spartan-3AN series FPGA, which has its own non-volatile Flash, with a capacity of up to 11Mb, and plenty of space to store protected data. The use of this built-in Flash FPGA not only saves cost, reduces PCB layout area, but also reduces power consumption compared to using two discrete devices, which is especially important for power supply after power-down.
存储子系统是Flash,Flash作为一种非易失性存储器,可以对最小单位一页(256Bytes)的地址空间进行擦除和再编程。在对存储空间进行编程之前需要进行擦除操作。相对于写入操作来说,擦除操作耗时较长。以Spartan-3AN内置Flash为例,擦除一页耗时约32~35毫秒,写一页耗时4~6毫秒。本发明采用预先擦除的方式,保证在掉电之后FPGA只需要对已擦除的地址进行写入操作,由处理器单元控制FPGA来实现预先擦除。当电源波动超过阈值,FPGA收到掉电指示信号为低电平,启动Flash写操作。 The storage subsystem is Flash, a non-volatile memory that can erase and reprogram the address space of a minimum of one page (256 Bytes). An erase operation is required before programming the memory space. The erase operation takes a long time relative to the write operation. Taking the Spartan-3AN built-in Flash as an example, erasing a page takes about 32 to 35 milliseconds, and writing a page takes 4 to 6 milliseconds. The invention adopts a pre-erase method to ensure that the FPGA only needs to write to the erased address after the power is turned off, and the processor unit controls the FPGA to implement the pre-erase. When the power supply fluctuates beyond the threshold, the FPGA receives the power-down indication signal to a low level and initiates a Flash write operation.
可选地,所述电信号为电压;所述第一指示信号为高电平;所述第二指示信号为低电平。Optionally, the electrical signal is a voltage; the first indication signal is a high level; and the second indication signal is a low level.
电压监测单元02包括:The voltage monitoring unit 02 includes:
掉电指示模块021,设置为采用电压作为所述电信号,当监测到电压的波动在阈值范围内时,输出的掉电指示信号是高电平,当监测到电压波动超过阈值范围时,输出的掉电指示信号是低电平。The power-down indication module 021 is configured to adopt a voltage as the electrical signal. When the fluctuation of the monitored voltage is within a threshold range, the output power-down indication signal is a high level, and when the monitored voltage fluctuation exceeds a threshold range, the output is output. The power down indication signal is low.
可选地,该装置还包括:储能电容05。Optionally, the device further includes: a storage capacitor 05.
处理器单元03,设置为将系统软件运行时产生且需要保护的状态数据、运算数据和内存数据均写入FPGA内部寄存器或者内部随机存储器;以及,将当前系统时间写入FPGA内部寄存器,FPGA启动内部系统计时,等待电源发生掉电。The processor unit 03 is configured to write state data, operation data and memory data generated when the system software is running and needs to be protected into the FPGA internal register or the internal random access memory; and write the current system time into the FPGA internal register, and the FPGA starts The internal system is timed and waits for the power to be powered down.
储能电容05,设置为在电源发生掉电之后,对FPGA供电。The storage capacitor 05 is set to supply power to the FPGA after the power supply has been powered down.
FPGA 04,还设置为在系统掉电后将所述状态数据、运算数据、内存数据和掉电时系统时间写入非易失性闪存Flash。FPGA 04 is also configured to write the status data, operational data, memory data, and system time at power down to the non-volatile flash memory after the system is powered down.
可选地,Optionally,
处理器单元03,设置为当监测到输出所述第二指示信号时,如归哦电源未实际掉电,且电子设备的系统软件的工作未受影响,则控制现场可编程门阵列单元FPGA擦除Flash中的相应地址,再次等待电源发生掉电。The processor unit 03 is configured to: when the second indication signal is detected to be output, if the power supply is not actually powered down, and the operation of the system software of the electronic device is not affected, then the field programmable gate array unit FPGA wipe is controlled. In addition to the corresponding address in Flash, wait for the power supply to power down again.
电源单元01,输出电压VO高于FPGA正常工作电压下限值VL,低于上限值VH,阈值设置在电源输出电压VO和FPGA正常工作的电压下限电压VL之间。这样当系统掉电时,储能电容能够以高于FPGA正常工作所需的最小电压开始供电。阈值与储能电容的容量需要达到一种平衡,保证既不会因为阈值设置过高引起误操作,也不会因为储能电容过大增加成本和布板面积。The power supply unit 01 has an output voltage VO higher than the lower limit value VL of the normal operating voltage of the FPGA, which is lower than the upper limit value VH, and the threshold is set between the power supply output voltage VO and the lower voltage VL of the normal operation of the FPGA. Thus, when the system is powered down, the storage capacitor can begin to supply power at a minimum voltage that is higher than the normal operation of the FPGA. The threshold and the capacity of the storage capacitor need to be balanced to ensure that the threshold is not set too high and the operation is not caused, and the storage capacity is not increased because the storage capacitor is too large.
可选地,现场可编程门阵列单元FPGA 04,还设置为在电子设备启动后,FPGA将上次掉电后保存在所述Flash中的状态数据、运算数据和内存数据读入FPGA内部寄存器或者内部随机存储器。Optionally, the field programmable gate array unit FPGA 04 is further configured to: after the electronic device is started, the FPGA reads the state data, the operation data, and the memory data stored in the Flash after the last power-down, into the FPGA internal register or Internal random access memory.
处理器单元03还设置为,通过数据读取通道读取FPGA的内部寄存器或者内部随机存储器,恢复所述数据。The processor unit 03 is further arranged to read the internal registers of the FPGA or the internal random access memory through the data read channel to recover the data.
FPGA 04还设置为,通过数据读取通道读取数据完毕后,将Flash中与所 述数据对应的地址空间擦除。FPGA 04 is also set to read the data through the data read channel, then the Flash will be The address space corresponding to the data is erased.
本发明实施例还提供了一种电子设备,包括上述的掉电保护的装置,如图4所示,掉电保护的装置包括:电源单元01、电压监测单元02、处理器单元03、现场可编程门阵列单元FPGA 04;The embodiment of the present invention further provides an electronic device, including the above device for power failure protection. As shown in FIG. 4, the device for power failure protection includes: a power supply unit 01, a voltage monitoring unit 02, a processor unit 03, and an on-site Programming gate array unit FPGA 04;
电压监测单元02,设置为监测电源输出的电信号,当所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号;The voltage monitoring unit 02 is configured to monitor an electrical signal output by the power source, and when the fluctuation of the electrical signal is within a threshold range, output a first indication signal as a power failure indication signal, when the fluctuation of the electrical signal exceeds the threshold range Outputting a second indication signal as a power down indication signal;
现场可编程门阵列单元FPGA 04,设置为当出现第二指示信号时,将与处理器单元同步的数据和当前系统时间写入非易失性闪存Flash,并在所述电子设备下一次上电后加载。The field programmable gate array unit FPGA 04 is configured to write the data synchronized with the processor unit and the current system time to the non-volatile flash memory when the second indication signal is present, and power on the electronic device next time. After loading.
采用本方案之后的优势是:掉电后在处理器单元外部执行数据的存储,减少了掉电后处理器单元和操作系统的操作,较纯软件保护方法更快速,能够保证在电源意外掉电的环境下将数据安全地记录下来,节省电量且能够即时存储数据。The advantage after adopting this scheme is that the data storage is performed outside the processor unit after power-off, which reduces the operation of the processor unit and the operating system after power-off, and is faster than the pure software protection method, and can ensure that the power supply is unexpectedly powered down. The data is safely recorded, saving power and enabling instant storage of data.
一种计算机可读存储介质,存储有计算机可执行指令,所述计算机可执行指令被处理器执行时实现所述的掉电保护方法。A computer readable storage medium storing computer executable instructions that, when executed by a processor, implement the power down protection method.
本领域普通技术人员可以理解上述实施例的全部或部分步骤可以使用计算机程序流程来实现,所述计算机程序可以存储于一计算机可读存储介质中,所述计算机程序在相应的硬件平台上(如系统、设备、装置、器件等)执行,在执行时,包括方法实施例的步骤之一或其组合。One of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described embodiments can be implemented using a computer program flow, which can be stored in a computer readable storage medium, such as on a corresponding hardware platform (eg, The system, device, device, device, etc. are executed, and when executed, include one or a combination of the steps of the method embodiments.
可选地,上述实施例的全部或部分步骤也可以使用集成电路来实现,这些步骤可以被分别制作成一个个集成电路模块,或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。Alternatively, all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
上述实施例中的装置/功能模块/功能单元可以采用通用的计算装置来实现,它们可以集中在单个的计算装置上,也可以分布在多个计算装置所组成的网络上。The devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
上述实施例中的装置/功能模块/功能单元以软件功能模块的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储介质中。上述提到的计算机可读取存储介质可以是只读存储器,磁盘或光盘等。 When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. The above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
工业实用性Industrial applicability
本发明实施例方案掉电后在处理器单元外部执行数据的存储,减少了掉电后处理器单元和操作系统的操作,较纯软件保护方法更快速,能够保证在电源意外掉电的环境下将数据安全地记录下来,节省电量且能够即时存储数据。 The device of the embodiment of the invention performs data storage outside the processor unit after power-off, which reduces the operation of the processor unit and the operating system after power-off, and is faster than the pure software protection method, and can ensure the environment in the case of unexpected power failure. Record data securely, conserve power and store data instantly.

Claims (14)

  1. 一种掉电保护的方法,应用于电子设备,所述电子设备包括现场可编程门阵列单元FPGA,所述方法包括:A method of power-down protection is applied to an electronic device, the electronic device comprising a field programmable gate array unit FPGA, the method comprising:
    监测电源输出的电信号;当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号;Monitoring an electrical signal output by the power source; when monitoring that the fluctuation of the electrical signal is within a threshold range, outputting a first indication signal as a power down indication signal, when detecting that the fluctuation of the electrical signal exceeds the threshold range, Outputting a second indication signal as a power down indication signal;
    当监测到输出所述第二指示信号时,将与处理器单元同步的数据和当前系统时间写入非易失性闪存Flash,并在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据。When the second indication signal is detected to be output, the data synchronized with the processor unit and the current system time are written into the non-volatile flash memory, and the stored storage is loaded after the electronic device is powered on next time. The data that the processor unit synchronizes.
  2. 根据权利要求1所述的掉电保护方法,其中,所述电信号为电压;所述第一指示信号为高电平;所述第二指示信号为低电平;The power-down protection method according to claim 1, wherein the electrical signal is a voltage; the first indication signal is a high level; and the second indication signal is a low level;
    当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号包括:When it is detected that the fluctuation of the electrical signal is within a threshold range, outputting a first indication signal as a power-down indication signal, and when detecting that the fluctuation of the electrical signal exceeds the threshold range, outputting as a power-down indication signal The second indication signal includes:
    当监测到所述电压的波动在所述阈值范围内时,输出高电平,当监测到所述电压的波动超过阈值范围时,输出低电平。When it is detected that the fluctuation of the voltage is within the threshold range, a high level is output, and when it is detected that the fluctuation of the voltage exceeds a threshold range, a low level is output.
  3. 根据权利要求1所述的掉电保护方法,其中,所述电信号的波动超过所述阈值范围包括:电源输出的电信号向下波动超过所述阈值范围的下限阈值。The power-down protection method according to claim 1, wherein the fluctuation of the electrical signal exceeding the threshold range comprises that an electrical signal output by the power source fluctuates downward beyond a lower threshold of the threshold range.
  4. 根据权利要求1所述的掉电保护方法,其中,将与处理器单元同步的数据和当前系统时间写入非易失性闪存Flash包括:The power-down protection method of claim 1, wherein writing data synchronized with the processor unit and current system time to the non-volatile flash memory comprises:
    由所述处理器单元将系统软件运行时产生且需要保护的状态数据、运算数据和内存数据均写入FPGA内部寄存器或者内部随机存储器;以及,由所述处理器单元将当前系统时间写入FPGA内部寄存器,FPGA启动内部系统计时,等待电源发生掉电;State data, operation data, and memory data generated by the system software and required to be protected by the processor unit are written into an FPGA internal register or an internal random access memory; and the current system time is written into the FPGA by the processor unit Internal registers, the FPGA starts the internal system timing, waiting for the power to be powered down;
    电源发生掉电之后,由储能电容对FPGA供电,由FPGA在系统掉电后将所述状态数据、运算数据、内存数据和掉电时系统时间写入FPGA内置的非易失性闪存Flash。 After the power supply is powered off, the FPGA is powered by the storage capacitor. The FPGA writes the status data, operation data, memory data, and system time at power-down to the non-volatile flash memory built into the FPGA after the system is powered down.
  5. 根据权利要求1所述的掉电保护方法,所述方法还包括:当监测到输出所述第二指示信号时,如果电源未实际掉电,且电子设备的软件的工作未受影响,则由处理器单元控制FPGA擦除非易失性闪存中的相应地址,再次等待电源发生掉电。The power-down protection method according to claim 1, further comprising: when monitoring the output of the second indication signal, if the power source is not actually powered down, and the operation of the software of the electronic device is not affected, The processor unit controls the FPGA to erase the corresponding address in the non-volatile flash and waits again for the power to be powered down.
  6. 根据权利要求1所述的掉电保护方法,所述在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据包括:The power-down protection method according to claim 1, wherein the loading of the stored data synchronized with the processor unit after the next power-on of the electronic device comprises:
    在所述电子设备启动后,所述FPGA将上次掉电后保存在所述非易失性闪存中的被保护数据读入FPGA内部寄存器或者内部随机存储器,由所述处理器单元通过数据读取通道读取所述FPGA的内部寄存器或者内部随机存储器,恢复所述数据;After the electronic device is started, the FPGA reads the protected data saved in the non-volatile flash memory after the last power-down into the FPGA internal register or the internal random access memory, and the processor unit reads the data through the data. Taking a channel to read an internal register of the FPGA or an internal random access memory to recover the data;
    通过所述数据读取通道读取数据完毕后,所述FPGA将所述Flash中与所述数据对应的地址空间擦除。After the data is read by the data read channel, the FPGA erases an address space corresponding to the data in the flash.
  7. 一种掉电保护的装置,应用于电子设备,所述装置包括:电压监测单元、现场可编程门阵列单元FPGA和处理器单元;A device for power failure protection is applied to an electronic device, the device comprising: a voltage monitoring unit, a field programmable gate array unit FPGA and a processor unit;
    所述电压监测单元,设置为监测电源输出的电信号;当监测到所述电信号的波动处于阈值范围内时,输出作为掉电指示信号的第一指示信号,当监测到所述电信号的波动超过所述阈值范围时,输出作为掉电指示信号的第二指示信号;The voltage monitoring unit is configured to monitor an electrical signal output by the power source; when it is detected that the fluctuation of the electrical signal is within a threshold range, outputting a first indication signal as a power failure indication signal, when the electrical signal is detected When the fluctuation exceeds the threshold range, outputting a second indication signal as a power down indication signal;
    所述FPGA,设置为当检测到输出所述第二指示信号时,将与所述处理器单元同步的数据和当前系统时间写入非易失性闪存Flash,并在所述电子设备下一次上电后加载存储的所述与处理器单元同步的数据。The FPGA is configured to, when detecting the outputting the second indication signal, write data synchronized with the processor unit and current system time to a non-volatile flash memory, and on the electronic device next time The stored data synchronized with the processor unit is loaded after being powered.
  8. 根据权利要求7所述的掉电保护装置,其中,所述电信号为电压;所述第一指示信号为高电平;所述第二指示信号为低电平;The power-down protection device according to claim 7, wherein the electrical signal is a voltage; the first indication signal is a high level; and the second indication signal is a low level;
    所述电压监测单元包括:The voltage monitoring unit includes:
    掉电指示模块,设置为当监测到所述电压的波动在所述阈值范围内时,输出高电平,当监测到所述电压的波动超过阈值范围时,输出低电平。The power-down indicating module is configured to output a high level when the fluctuation of the voltage is detected within the threshold range, and output a low level when the fluctuation of the voltage is detected to exceed a threshold range.
  9. 根据权利要求7所述的掉电保护装置,其中,所述电信号的波动超过所述阈值范围包括:电源输出的电信号向下波动超过所述阈值范围的下限阈值。 The power-down protection device of claim 7, wherein the fluctuation of the electrical signal exceeds the threshold range comprises: an electrical signal output by the power supply fluctuating downwardly beyond a lower threshold of the threshold range.
  10. 根据权利要求7所述的掉电保护装置,所述装置还包括:储能电容;The power-down protection device of claim 7, further comprising: a storage capacitor;
    处理器单元,设置为将系统软件运行时产生的被保护数据均写入FPGA内部寄存器或者内部随机存储器;以及,将当前系统时间写入FPGA内部寄存器,FPGA启动内部系统计时,等待电源发生掉电;The processor unit is configured to write the protected data generated when the system software is running into the FPGA internal register or the internal random access memory; and, write the current system time into the FPGA internal register, and the FPGA starts the internal system timing, waiting for the power supply to be powered down. ;
    储能电容,设置为在电源发生掉电之后,对FPGA供电;The storage capacitor is set to supply power to the FPGA after the power supply is powered down;
    FPGA,还设置为在系统掉电后将所述状态数据、运算数据、内存数据和掉电时系统时间写入非易失性闪存Flash。The FPGA is also configured to write the state data, the operational data, the memory data, and the system time at the time of power down to the non-volatile flash memory after the system is powered down.
  11. 根据权利要求7所述的掉电保护装置,所述处理器单元,设置为当监测到输出所述第二指示信号时,如果电源未实际掉电,且电子设备的软件的工作未受影响,则控制所述FPGA擦除非易失性闪存中的相应地址,再次等待电源发生掉电。The power-down protection device according to claim 7, wherein the processor unit is configured to, when the second indication signal is outputted, if the power source is not actually powered down, and the operation of the software of the electronic device is not affected, Then the FPGA is controlled to erase the corresponding address in the non-volatile flash memory, and wait for the power supply to be powered down again.
  12. 根据权利要求11所述的掉电保护装置,其特征在于,The power failure protection device according to claim 11, wherein
    所述FPGA还设置为,在电子设备启动后,FPGA将上次掉电后保存在所述非易失性闪存中的被保护数据读入FPGA内部寄存器或者内部随机存储器;The FPGA is further configured to: after the electronic device is started, the FPGA reads the protected data stored in the non-volatile flash memory after the last power-down into the FPGA internal register or the internal random access memory;
    所述处理器单元还设置为,通过数据读取通道读取所述FPGA的内部寄存器或者内部随机存储器,恢复所述数据;The processor unit is further configured to read an internal register of the FPGA or an internal random access memory through a data read channel to recover the data;
    所述FPGA还设置为,通过所述数据读取通道读取数据完毕后,将所述Flash中与所述数据对应的地址空间擦除。The FPGA is further configured to erase the address space corresponding to the data in the Flash after the data is read by the data read channel.
  13. 一种电子设备,包括权利要求7~12任意一项中的掉电保护的装置。An electronic device comprising the device for power-down protection according to any one of claims 7 to 12.
  14. 一种计算机可读存储介质,存储有计算机可执行指令,所述计算机可执行指令被处理器执行时实现权利要求1至6任意一项所述的掉电保护方法。 A computer readable storage medium storing computer executable instructions that, when executed by a processor, implement the power down protection method of any one of claims 1 to 6.
PCT/CN2016/084168 2015-09-30 2016-05-31 Power-down protection method and apparatus, and electronic device WO2017054487A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510638542.6 2015-09-30
CN201510638542.6A CN106557438A (en) 2015-09-30 2015-09-30 A kind of method of power down protection, device and electronic equipment

Publications (1)

Publication Number Publication Date
WO2017054487A1 true WO2017054487A1 (en) 2017-04-06

Family

ID=58418059

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/084168 WO2017054487A1 (en) 2015-09-30 2016-05-31 Power-down protection method and apparatus, and electronic device

Country Status (2)

Country Link
CN (1) CN106557438A (en)
WO (1) WO2017054487A1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109188990A (en) * 2018-11-12 2019-01-11 苏州易德龙科技股份有限公司 A kind of power failure detection method and system
CN109597773A (en) * 2018-12-10 2019-04-09 浪潮(北京)电子信息产业有限公司 A kind of SSD and its method for power fail safeguard of data, system, device
CN112116942A (en) * 2019-06-21 2020-12-22 北京自动化控制设备研究所 Circuit for performing segmented protection on FLASH by utilizing FPGA
CN112579484A (en) * 2019-09-29 2021-03-30 北京声智科技有限公司 Power-down state protection method and device for intelligent sound box and main board power supply circuit
CN112652348A (en) * 2020-12-22 2021-04-13 深圳市国微电子有限公司 NAND Flash chip power-down protection circuit and protection method
CN113110880A (en) * 2020-01-10 2021-07-13 中移物联网有限公司 System starting method and electronic equipment
CN113687710A (en) * 2021-10-26 2021-11-23 西安羚控电子科技有限公司 Power failure processing method and system for flight control management computer of fixed-wing unmanned aerial vehicle
CN114546094A (en) * 2022-02-25 2022-05-27 苏州浪潮智能科技有限公司 Method, system, equipment and storage medium for abnormal power failure test of SSD (solid State disk) equipment
CN115079803A (en) * 2022-05-20 2022-09-20 上海瑞浦青创新能源有限公司 Abnormal power failure data storage device suitable for microcontroller
WO2023108829A1 (en) * 2021-12-13 2023-06-22 上海御渡半导体科技有限公司 Device and method for collecting information before power failure of test head
WO2023193545A1 (en) * 2022-04-06 2023-10-12 上海美仁半导体有限公司 Power-failure protection method and apparatus for chip, and chip and storage medium
CN117420962A (en) * 2023-12-14 2024-01-19 深圳市德兰明海新能源股份有限公司 Data access management method, single chip microcomputer product and storage medium
CN112652348B (en) * 2020-12-22 2024-03-22 深圳市国微电子有限公司 NAND Flash chip power-down protection circuit and protection method

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107341075B (en) * 2017-08-28 2023-12-15 北京世通凌讯科技有限公司 Power-down protection device and electronic equipment
CN108446009A (en) * 2018-03-10 2018-08-24 北京联想核芯科技有限公司 Power down control method, device, equipment and medium
JP6904918B2 (en) * 2018-03-29 2021-07-21 ファナック株式会社 Control device and its data writing method
CN109188122A (en) * 2018-08-11 2019-01-11 武汉盛硕电子有限公司 A kind of power-failure memory method for charging pile
US11295792B2 (en) 2019-09-30 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Back-up and restoration of register data
CN111078486B (en) * 2019-12-11 2022-05-24 成都华大九天科技有限公司 Method for simulating power failure of storage in FPGA
CN110750390B (en) * 2019-12-20 2020-04-17 浙江中控太阳能技术有限公司 Method and device for storing angle value of heliostat in case of power failure
CN111140529B (en) * 2019-12-24 2022-03-29 追觅科技(上海)有限公司 Blower control method, blower control device and storage medium
CA3156378A1 (en) * 2019-12-24 2021-07-01 Hao Yu Hairdryer control method, device and storage medium
CN112542204A (en) * 2020-12-29 2021-03-23 深圳市芯天下技术有限公司 Low-voltage alarm method and device for nonvolatile chip, storage medium and terminal
CN112929013B (en) * 2021-02-01 2023-07-25 四川爱创科技有限公司 Circuit for realizing power-down self-recovery memory function and control method thereof
CN113742166B (en) * 2021-07-29 2023-07-18 苏州浪潮智能科技有限公司 Method, device and system for recording logs of server system devices
CN113765183A (en) * 2021-09-01 2021-12-07 长春捷翼汽车零部件有限公司 Charging device with automatic power failure memory function, working method, equipment, medium and vehicle
CN116745768A (en) * 2022-01-10 2023-09-12 华为技术有限公司 Data processing method and electronic equipment
CN114993540A (en) * 2022-08-02 2022-09-02 国网江西省电力有限公司建设分公司 Data acquisition, protection and storage device for tension sensor
CN115963913A (en) * 2023-03-17 2023-04-14 合肥联宝信息技术有限公司 Real-time clock power supply method, power supply circuit and storage medium

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101010668A (en) * 2004-09-02 2007-08-01 英特尔公司 Volatile storage based power loss recovery mechanism
US20090172469A1 (en) * 2007-12-27 2009-07-02 Huawei Technologies Co., Ltd. Method, apparatus, logic device and storage system for power-fail protection
CN102622257A (en) * 2012-04-25 2012-08-01 钜泉光电科技(上海)股份有限公司 On-line meter self-updating method and device
CN103984610A (en) * 2014-06-11 2014-08-13 武汉邮电科学研究院 FPGA (Field Programmable Gate Array) based power failure protection system and method
CN104035893A (en) * 2014-06-30 2014-09-10 浪潮(北京)电子信息产业有限公司 Method for data storage during abnormal power down of computer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8325554B2 (en) * 2008-07-10 2012-12-04 Sanmina-Sci Corporation Battery-less cache memory module with integrated backup
CN104021093A (en) * 2014-06-24 2014-09-03 浪潮集团有限公司 Power-down protection method for memory device based on NVDIMM (non-volatile dual in-line memory module)

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101010668A (en) * 2004-09-02 2007-08-01 英特尔公司 Volatile storage based power loss recovery mechanism
US20090172469A1 (en) * 2007-12-27 2009-07-02 Huawei Technologies Co., Ltd. Method, apparatus, logic device and storage system for power-fail protection
CN102622257A (en) * 2012-04-25 2012-08-01 钜泉光电科技(上海)股份有限公司 On-line meter self-updating method and device
CN103984610A (en) * 2014-06-11 2014-08-13 武汉邮电科学研究院 FPGA (Field Programmable Gate Array) based power failure protection system and method
CN104035893A (en) * 2014-06-30 2014-09-10 浪潮(北京)电子信息产业有限公司 Method for data storage during abnormal power down of computer

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109188990A (en) * 2018-11-12 2019-01-11 苏州易德龙科技股份有限公司 A kind of power failure detection method and system
CN109597773B (en) * 2018-12-10 2024-01-23 浪潮(北京)电子信息产业有限公司 SSD and data power-down protection method, system and device thereof
CN109597773A (en) * 2018-12-10 2019-04-09 浪潮(北京)电子信息产业有限公司 A kind of SSD and its method for power fail safeguard of data, system, device
CN112116942A (en) * 2019-06-21 2020-12-22 北京自动化控制设备研究所 Circuit for performing segmented protection on FLASH by utilizing FPGA
CN112116942B (en) * 2019-06-21 2023-04-07 北京自动化控制设备研究所 Circuit for performing segmented protection on FLASH by utilizing FPGA
CN112579484A (en) * 2019-09-29 2021-03-30 北京声智科技有限公司 Power-down state protection method and device for intelligent sound box and main board power supply circuit
CN113110880A (en) * 2020-01-10 2021-07-13 中移物联网有限公司 System starting method and electronic equipment
CN112652348A (en) * 2020-12-22 2021-04-13 深圳市国微电子有限公司 NAND Flash chip power-down protection circuit and protection method
CN112652348B (en) * 2020-12-22 2024-03-22 深圳市国微电子有限公司 NAND Flash chip power-down protection circuit and protection method
CN113687710A (en) * 2021-10-26 2021-11-23 西安羚控电子科技有限公司 Power failure processing method and system for flight control management computer of fixed-wing unmanned aerial vehicle
CN113687710B (en) * 2021-10-26 2022-03-22 西安羚控电子科技有限公司 Power failure processing method and system for flight control management computer of fixed-wing unmanned aerial vehicle
WO2023108829A1 (en) * 2021-12-13 2023-06-22 上海御渡半导体科技有限公司 Device and method for collecting information before power failure of test head
CN114546094A (en) * 2022-02-25 2022-05-27 苏州浪潮智能科技有限公司 Method, system, equipment and storage medium for abnormal power failure test of SSD (solid State disk) equipment
CN114546094B (en) * 2022-02-25 2023-08-11 苏州浪潮智能科技有限公司 Method, system, device and storage medium for detecting abnormal power failure of SSD device
WO2023193545A1 (en) * 2022-04-06 2023-10-12 上海美仁半导体有限公司 Power-failure protection method and apparatus for chip, and chip and storage medium
CN115079803A (en) * 2022-05-20 2022-09-20 上海瑞浦青创新能源有限公司 Abnormal power failure data storage device suitable for microcontroller
CN117420962A (en) * 2023-12-14 2024-01-19 深圳市德兰明海新能源股份有限公司 Data access management method, single chip microcomputer product and storage medium

Also Published As

Publication number Publication date
CN106557438A (en) 2017-04-05

Similar Documents

Publication Publication Date Title
WO2017054487A1 (en) Power-down protection method and apparatus, and electronic device
US8009499B2 (en) Providing a capacitor-based power supply to enable backup copying of data from volatile storage to persistent storage
KR101844206B1 (en) Solid state drive with self-refresh power-saving mode
US9250820B2 (en) Power efficient method for cold storage data retention management
US8093868B2 (en) In situ verification of capacitive power support
US8060767B1 (en) Ultra low power sleep mode
JP6018113B2 (en) Method, computer and host device for preventing data loss of nonvolatile memory
US8874839B2 (en) Electronic system and method and apparatus for saving data thereof
TWI529738B (en) Flash -backed dram module with state of health and or status information available through a configuration data bus
TW201351117A (en) State control device, information processing device, computer program product, and semiconductor device
US10394307B2 (en) Information processing apparatus, information processing method, and program
US20170062041A1 (en) Memory control circuit for controlling memory device that operates in self-refresh mode, and method of controlling the same
US10831657B2 (en) Debug data recovery after PLI event
JP2015118423A (en) Refresh device and electronic apparatus
JP2008225929A (en) Information processor
JP5795758B2 (en) Method for protecting data in non-volatile storage device
JP5807495B2 (en) Communication data logger device
JP2017021498A (en) Control system and controller therefor
JP2010117752A (en) Data holding method of electronic equipment and electronic equipment
CN111192607A (en) Power-down protection method and device for storage system and related components
JP2006318105A (en) Monitoring system
US20230376381A1 (en) Checkpoint-progress status
EP4202686A1 (en) Terminal device
JPH0934805A (en) Semiconductor disk device
JP2005149451A (en) Semiconductor disk device and disk device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16850112

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16850112

Country of ref document: EP

Kind code of ref document: A1